ADSP-21065 Analog Devices, ADSP-21065 Datasheet - Page 30

• Manufacturer Part Number: ADSP-21065
• Description: DSP Microcomputer
• Manufacturer: Analog Devices

ADSP-21065L
SDRAM Interface—Bus Master
Use these specifications for ADSP-21065L bus master accesses of SDRAM.
Parameter
Timing Requirements:
t
t
Switching Characteristics:
t
t
t
t
t
t
t
t
t
t
t
t
t
NOTES
1
2
SDRAM Interface—Bus Slave
These timing requirements allow a bus slave to sample the bus master’s SDRAM command and detect when a refresh occurs.
Parameter
Timing Requirements:
t
t
t
t
NOTE
1
Command = SDCKE, MSx, RAS, CAS, SDWE, DQM, and SDA10.
SDRAM controller adds one SDRAM CLK three-stated cycle delay (t
Command = SDCKE, RAS, CAS, and SDWE.
SDSDK
HDSDK
DSDK1
DSDK2
SDK
SDKH
SDKL
DCADSDK
HCADSDK
SDTRSDK
SDENSDK
SDCTR
SDCEN
SDATR
SDAEN
SSDKC1
SSDKC2
SCSDK
HCSDK
Data Setup Before SDCLK
Data Hold After SDCLK
First SDCLK Rise Delay After CLKIN
Second SDCLK Rise Delay After CLKIN
SDCLK Period
SDCLK Width High
SDCLK Width Low
Command, Address, Data, Delay After SDCLK
Command, Address, Data, Hold After SDCLK
Data Three-State After SDCLK
Data Enable After SDCLK
SDCLK, Command Three-State After CLKIN
SDCLK, Command Enable After CLKIN
Address Three-State After CLKIN
Address Enable After CLKIN
First SDCLK Rise After CLKIN
Second SDCLK Rise After CLKIN
Command Setup Before SDCLK
Command Hold After SDCLK
2
1
1
CK
/2) on a Read followed by a Write.
1
1
1
1
Min
2.0
1.25
9.0 + 6 DT
25.5 + 22 DT
16.67
7.5 + 8 DT
6.5 + 8 DT
4.5 + 5 DT
6.0 + 5 DT
5.0 + 3 DT
5.0 + 2 DT
–1.0 – 4 DT
1.0 – 2 DT
Min
6.50 + 16 DT
0.0
2.0
23.25
Max
12.75 + 6 DT
29.25 + 22 DT
t
10.0 + 5 DT
9.5 + 5 DT
9.75 + 3 DT
10.0 + 2 DT
3.0 – 4 DT
7.0 – 2 DT
Max
17.5 + 16 DT
34.25
CK
/2
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns