ADSP-2171 Analog Devices, ADSP-2171 Datasheet - Page 10

• Manufacturer Part Number: ADSP-2171
• Description: ADSP-2100 Family DSP Microcomputers
• Manufacturer: Analog Devices

ADSP-2171/ADSP-2172/ADSP-2173
Bus Request & Bus Grant
The ADSP-217x can relinquish control of the data and address
buses to an external device. When the external device requires
access to memory, it asserts the bus request (BR) signal. If the
ADSP-217x is not performing an external memory access, then
it responds to the active BR input in the following processor
cycle by:
If the Go Mode is enabled, the ADSP-217x will not halt pro-
gram execution until it encounters an instruction that requires
an external memory access.
If the ADSP-217x is performing an external memory access
when the external device asserts the BR signal, then it will not
three-state the memory interfaces or assert the BG signal until
the processor cycle after the access completes, which can be up
to eight cycles later depending on the number of wait states.
The instruction does not need to be completed when the bus is
granted. If a single instruction requires two external memory ac-
cesses, the bus will be granted between the two accesses.
When the BR signal is released, the processor releases the BG
signal, reenables the output drivers and continues program ex-
ecution from the point where it stopped.
The bus request feature operates at all times, including when
the processor is booting and when RESET is active.
The new Bus Grant Hang logic and associated BGH pin allow
the ADSP-217x to operate in a multiprocessor environment
with a minimal number of “wasted” processor cycles. The bus
grant hang pin is asserted when the ADSP-217x desires a cycle,
three-stating the data and address buses and the PMS, DMS,
asserting the bus grant (BG) signal, and
halting program execution.
BMS, RD, WR output drivers,
AX0
I0
I1
I2
I3
DAG 1
M0
M1
M2
M3
AX1
AR
ALU
L0
L1
L2
L3
AY0
AF
AY1
I4
I5
I6
I7
DAG 2
M4
M5
M6
M7
MX0 MX1 MY0 MY1
MR0 MR1
L4
L5
L6
L7
MAC
OWRCNTR
MR2
COUNT
STACK
SSTAT
CNTR
4 X 14
PROGRAM SEQUENCER
MF
Figure 7. ADSP-217x Registers Control Register
STATUS
MSTAT
ASTAT
STACK
12 X 25
IMASK
ICNTL
IFC
SI
SHIFTER
SR0 SR1
SE
SB
STACK
16 X 14
STACK
4 X 18
LOOP
PC
14
14
24
16
PMA BUS
DMA BUS
DMD BUS
PMD BUS
0x3FFF
0x3FFE
CONTROL REGISTERS
0x3FFA-0x3FF3
–10–
SPORT 0
PX
RX0 TX0
SYSTEM CONTROL
DM WAIT CONTROL
but cannot execute it because the bus is granted to some other
processor. With the BGH signal, the other processor(s) in the
system can be alerted that the ADSP-217x is hung and release
the bus by deasserting bus request. Once the bus is released the
ADSP-217x executes the external access and deasserts BGH.
This is a signal to the other processors that external memory is
now available.
ADSP-217X REGISTERS
Figure 7 summarizes all the registers in the ADSP-217x. Some
registers store values. For example, AX0 stores an ALU oper-
and; I4 stores a DAG2 pointer. Other registers consist of control
bits and fields, or status flags. For example, ASTAT contains
status flags from arithmetic operations, and fields in DWAIT
control the numbers of wait states for different zones of data
memory.
A secondary set of registers in all computational units allows a
single-cycle context switch.
The bit and field definitions for control and status registers are
given in the rest of this section, except for IMASK, ICNTL and
IFC, which are defined earlier in this data sheet. The system
control register, DWAIT register, timer registers, HIP control
registers, HIP data registers, and SPORT control registers are
all mapped into data memory; that is, registers are accessed by
reading and writing data memory locations rather than register
names. The particular data memory address is shown with each
memory-mapped register.
Register bit values shown on the following pages are the default
bit values after reset. If no values are shown, the bits are indeter-
minate at reset. Reserved bits are shown in gray; these bits
should always be written with zeros.
CONTROL REGISTERS
0x3FF2-0x3FEF
SPORT 1
RX1 TX1
PROGRAM
PROGRAM
2K X 24
8K X 24
SRAM
ROM
0x3FFD
0x3FFC
0x3FFB
2K X 16
DATA
SRAM
TIMER
TPERIOD
TCOUNT
TSCALE
0x3FE0-0x3FE5
0x3FE6-0x3FE7
0x3FE8
INTERFACE
POWERDOWN
HOST
PORT
CONTROL
LOGIC
DATA
STATUS
HMASK
FLAGS
REV. A