ADSP-2186 Analog Devices, ADSP-2186 Datasheet - Page 18

• Manufacturer Part Number: ADSP-2186
• Description: DSP Microcomputer
• Manufacturer: Analog Devices

ADSP-2186
Parameter
Bus Request–Bus Grant
Timing Requirements:
t
t
Switching Characteristics:
t
t
t
t
t
t
NOTES
xMS = PMS, DMS, CMS, IOMS, BMS.
1
2
BH
BS
SD
SDB
SE
SEC
SDBH
SEH
BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on
the following cycle. Refer to the ADSP-2100 Family User’s Manual, Third Edition, for BR/BG cycle relationships.
BGH is asserted when the bus is granted and the processor requires control of the bus to continue.
BR Hold after CLKOUT High
BR Setup before CLKOUT Low
CLKOUT High to xMS, RD, WR Disable
xMS, RD, WR Disable to BG Low
BG High to xMS, RD, WR Enable
xMS, RD, WR Enable to CLKOUT High
xMS, RD, WR Disable to BGH Low
BGH High to xMS, RD, WR Enable
PMS, DMS
CLKOUT
BMS, RD
CLKOUT
BGH
WR
BG
BR
t
Figure 13. Bus Request–Bus Grant
SD
t
BH
1
1
t
t
BS
t
SDBH
SDB
2
2
–18–
Min
0.25 t
0.25 t
0
0
0.25 t
0
0
CK
CK
CK
+ 2
+ 17
– 7
t
t
SEH
SE
t
SEC
Max
0.25 t
CK
+ 10
REV. A
Unit
ns
ns
ns
ns
ns
ns
ns
ns