SC486 Semtech Corporation, SC486 Datasheet - Page 12

• Manufacturer Part Number: SC486
• Description: Complete DDR1/2/3 Memory Power Supply
• Manufacturer: Semtech Corporation

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VDDQ Current Limit Circuit (Cont.)
The equation for the current limit threshold is as follows:
Where (referring to Figure 2) R
R
For resistor sensing, a sense resistor is placed between
the source of Q1 and PGND1. The current through the
source sense resistor develops a voltage that opposes
the voltage developed across R
developed across the R
drop across R
high side MOSFET will not be allowed to turn on. When
using an external sense resistor R
of the sense resistor.
The current limit circuitry also protects against negative
over-current (i.e. when the current is flowing from the
load to PGND1 through the inductor and bottom MOSFET).
In this case, when the bottom MOSFET is turned on, the
phase node, LX, will be higher than PGND initially. The
SC486 monitors the voltage at LX, and if it is greater
than a set threshold voltage of 125mV (nom.) the
bottom MOSFET is turned off. The device then waits for
approximately 2.5µs and then DL goes high for 300ns
(typ.) once more to sense the current. This repeats until
either the over-current condition goes away or the part
latches off due to output overvoltage (see Output
Overvoltage Protection).
I
POWER MANAGEMENT
LIMIT
DS(ON)
2006 Semtech Corp.
of the bottom of Q1.
10e
6 -
Figure 3: Valley Current Limiting
Valley Current-Limit Threshold Point
R
ILIM
R
SENSE
, a positive over-current exists and the
ILIM
A
SENSE
TIME
resistor reaches the voltage
ILIM
is R10 and R
ILIM
SENSE
. When the voltage
is the resistance
SENSE
I
I
I
PEAK
LOAD
LIMIT
is the
12
Power Good Output
The VDDQ output has its own power good output. Power
good is an open-drain output and requires a pull-up
resistor. When VDDQ is 16% above or 10% below its set
voltage, PGD gets pulled low. It is held low until the
output voltage returns to within these thresholds. PGD
is also held low during start-up and will not be allowed to
transition high until soft start is over (440 switching
cycles) and the output reaches 90% of its set voltage.
There is a 5µs delay built into the PGD circuitry to
prevent false transitions.
Output Overvoltage Protection
VDDQ: when the output exceeds 16% of its set
voltage the low-side MOSFET is latched on. It stays
latched on and the controller is latched off until reset
(see below). There is a 5µs delay built into the OV
protection circuit to prevent false transitions. An OV fault
in VDDQ will cause REF and VTT to turn off (high-Z) also
when VDDQ drops below 0.5V. Note: to reset from any
fault, VCCA or EN/PSV must be toggled.
VTT: when the output exceeds 12% of its set voltage the
output is latched in a tri-stated condition (high-Z). The
controller stays latched off until reset (see below). There
is a 50µs delay built into the OV protection circuit to
prevent false transitions. An OV fault in VTT will not
affect VDDQ or REF. To reset VTT from a fault, VCCA or
VTTEN or EN/PSV must be toggled.
Output Undervoltage Protection
VDDQ: when the output is 30% below its set voltage the
output is latched in a tri-stated condition. It stays latched
and the controller is latched off until reset (see below).
There is a 5µs delay built into the UV protection circuit to
prevent false transitions. An UV fault in VDDQ will cause
REF and VTT to turn off (high-Z) also when VDDQ drops
below 0.5V.
VTT: when the output is 12% below its set voltage the
output is latched in a tri-stated condition (high-Z). The
controller stays latched off until reset (see below). There
is a 50µs delay built into the UV protection circuit to
prevent false transitions. An UV fault in VTT will not
affect VDDQ or REF. To reset VTT from a fault, VCCA or
VTTEN or EN/PSV must be toggled.
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SC486