EPC2 Altera Corporation, EPC2 Datasheet
EPC2
Available stocks
Related parts for EPC2
EPC2 Summary of contents
Page 1
... IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface – Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1 – ISP circuitry is compatible with IEEE Std. 1532 for EPC2 configuration device – Supports programming through Serial Vector Format Files (.svf), Jam TM Standard Test and Programming Language (STAPL) Files ( ...
Page 2
... N. 20-Pin PLCC EPC1 EPC1441 EPC1213 EPC1064 EPC1064V Enhanced Sheet. Note ( N.C. 1 DCLK 2 N.C. 3 N.C. 4 N. 32-Pin TQFP EPC1441 EPC1064 EPC1064V Altera Corporation 24 N.C. 23 VCC 22 N.C. 21 N.C. 20 N.C. N. N.C. 17 N.C. ...
Page 3
... Figure 2. EPC2 Package Pin-Out Diagrams 3 2 DCLK 4 VCCSEL 5 6 N. 20-Pin PLCC Functional Description Altera Corporation Configuration Devices for SRAM-Based LUT Devices Data Sheet N.C. DCLK VCCSEL VPP N.C. 18 N.C. 17 N.C. N.C. N. VPPSEL 14 N. With SRAM-based devices, configuration data must be reloaded each time the system initializes, or when new configuration data is needed ...
Page 4
... EP20K100 (2.5 V) EP20K200 EP20K400 ACEX 1K EP1K10 (2.5 V) EP1K30 EP1K50 EP1K100 4 lists the configuration device used with each APEX II, APEX 20K, Data Size EPC1064 EPC1213 EPC1441 EPC1 EPC2 EPC4 EPC8 EPC16 (Bits) EPC1064V 4,714,000 6,276,000 9,612,000 17,390,000 1,297,000 4,383,000 1,964,000 3,901,000 5,564,000 8,938,000 347,000 ...
Page 5
... EPF8282A / 8000A EPF8282AV (5.0 V) (3.3 V) EPF8452A EPF8636A EPF8820A EPF81188A EPF1500A Altera Corporation Configuration Devices for SRAM-Based LUT Devices Data Sheet Data Size EPC1064 EPC1213 EPC1441 EPC1 EPC2 EPC4 EPC8 EPC16 (Bits) EPC1064V 470,000 785,000 785,000 1,336,000 1,840,000 2,757,000 2,757,000 120,000 1 402,000 621,000 ...
Page 6
... Figure 3: (1) Do not use EPC2 devices to configure FLEX 6000 devices. (2) The EPC1441, EPC1064, and EPC1064V devices do not support data cascading. The EPC2, EPC1, and EPC1213 devices support data cascading. (3) The OE pin is a bidirectional open-drain pin. 6 shows the configuration device block diagram. ...
Page 7
... DATA pin to avoid contention with other configuration devices. The EPC2 device allows the user to initiate configuration of the PLD via an additional pin, nINIT_CONF, that can be tied to the nCONFIG pin of the PLD( configured. A JTAG instruction causes the EPC4, EPC8, EPC16, and EPC2 device to drive nINIT_CONF low, which in turn pulls nCONFIG low ...
Page 8
... OE, nCS, and DCLK pins supply the control signals for the address counter and the output tri-state buffer. The configuration device sends a serial bitstream of configuration data to its DATA pin, which is routed to the DATA0 or DATA input pin on the LUT-based PLD device. an LUT-based PLD configured with a single EPC2, EPC1, or EPC1441 device. 8 Figure 4 ...
Page 9
... The pull-up resistor should be connected to the same supply voltage as the configuration device. All pull-up resistors are APEX 20KE pull up resistors are The OE, nCS, and nINIT_CONF pins on EPC2, EPC4, EPC8, and EPC16 devices have internal, user-configurable 1-k pull-up resistors. If internal pull-up resistors are used, external pull-up resistors should not be used on these pins ...
Page 10
... APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX device configuration. For information on EPC4, EPC8, and EPC16 devices, refer to Configuration Devices (EPC4, EPC8, & EPC16) Data Table 3. EPC2, EPC1, & EPC1441 Pin Functions During APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K & FLEX 6000 Configuration (Part Pin Name ...
Page 11
... Table 3. EPC2, EPC1, & EPC1441 Pin Functions During APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K & FLEX 6000 Configuration (Part Pin Name Pin Number 8-Pin 20-Pin PDIP (3) PLCC ( nCASC – 13 nINIT_CONF (5), (7) (7) – 11 TDI (7) – 1 TDO (7) – 19 TMS (7) – ...
Page 12
... Configuration Devices for SRAM-based LUT Devices Data Sheet Table 3. EPC2, EPC1, & EPC1441 Pin Functions During APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K & FLEX 6000 Configuration (Part Pin Name Pin Number 8-Pin 20-Pin PDIP (3) PLCC VCC 5 10 GND ...
Page 13
... The master EPC2 or EPC1 device clocks all subsequent slave devices until configuration is complete. Once all configuration data is transferred and the nCS pin on the master EPC2 or EPC1 device is driven high by the LUT- based PLD’s CONF_DONE pin, the master EPC2 or EPC1 device clocks 16 additional cycles to initialize the LUT-based PLD(s) ...
Page 14
... EPC4, EPC8, and EPC16 devices cannot be cascaded. (6) The nINIT_CONF pin is only available on EPC2 devices and has an internal pull that is always active. If nINIT_CONF is not available or not used, nCONFIG must be pulled to V (7) To ensure successful configuration between APEX 20KE and configuration devices in all possible power-up ...
Page 15
... CONF_DONE nCONFIG GND nCE Altera Corporation Configuration Devices for SRAM-Based LUT Devices Data Sheet Figure 6 shows two APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX devices configured with two EPC2 or EPC1 devices. Note (1) LUT-Based PLD (3) DCLK MSEL0 DATA0 MSEL1 nSTATUS CONF_DONE ...
Page 16
... EPC4, EPC8, and EPC16 devices cannot be cascaded. (5) The nINIT_CONF pin is only available on EPC2 devices and has an internal pull that is always active. If nINIT_CONF is not available or not used, nCONFIG must be pulled to V (6) To ensure successful configuration between APEX 20KE and configuration devices in all possible power-up ...
Page 17
... Configuration Devices for SRAM-Based LUT Devices Data Sheet Table 4 defines the APEX 20K, FLEX 10K, and FLEX 6000 timing parameters when using EPC2 devices at 3.3 V. Table 4. APEX 20K, FLEX 10K & FLEX 6000 Timing Parameters using EPC2 Devices at 3.3 V Note (1) Symbol ...
Page 18
... Enhanced Configuration Device (EPC4, EPC8 & EPC16) Data The configuration device imposes a POR delay upon initial power-up to allow the voltage supply to stabilize. Subsequent reconfigurations do not incur this delay. Note (1) Min 100 2 Altera Corporation Max Units 200 250 ns 250 ns ...
Page 19
... DCLK frequency CLK Notes to Table 6: (1) Do not use EPC16, EPC8, EPC4, or EPC2 devices to configure FLEX 6000 devices. (2) For more information regarding EPC4, EPC8, or EPC16 configuration device timing parameters, see the Enhanced Configuration Device (EPC4, EPC8 & EPC16) Data (3) The configuration device imposes a POR delay upon initial power-up to allow the voltage supply to stabilize ...
Page 20
... The pull-up resistor should be connected to the same supply voltage as the configuration device. All pull-up resistors are shows three FLEX 8000 devices configured with two EPC1 or shows a FLEX 8000 device (1) (1) VCC VCC (2) (2) Configuration Device nCS OE DATA DCLK Altera Corporation ...
Page 21
... MSEL0 DCLK DATA0 nCONFIG Notes to Figure 9: (1) The pull-resistor should be connected to the same supply voltage as the confiuration device. (2) All pull-up resistors are Altera Corporation Configuration Devices for SRAM-Based LUT Devices Data Sheet (1) (1) VCC VCC (2) (2) (1) (1) VCC VCC ...
Page 22
... DCLK clocks data out of the next device. 27 Power Power pin. 12 Ground Ground pin. A 0.2- F decoupling capacitor must be placed between the VCC and GND pins. Application Note 33 (Configuring FLEX 8000 Devices) Application Note 38 (Configuring Multiple FLEX 8000 Devices) Description Altera Corporation ...
Page 23
... During initial power-up, a POR delay occurs to permit voltage levels to stabilize. When configuring an APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, or FLEX 6000 device with an EPC4, EPC8, EPC16, EPC2, EPC1, or EPC1441 device, the POR delay occurs inside the configuration device, and the POR delay is a maximum of 200 ms. When configuring a ...
Page 24
... V . The EPC2 device’s VPPSEL pin must be set in accordance CC with the EPC2 VPP pin. If the VPP pin is supplied by a 5.0-V supply, VPPSEL must be connected to GND; if the VPP pin is supplied by a 3.3-V power supply, VPPSEL must be connected to V describes the relationship between the V Table 8. VCCSEL & ...
Page 25
... Low-Voltage I/O option in the Global Project Device Options dialog box (Assign menu) in the MAX+PLUS II software. Configuration Chain with Multiple Voltage Levels An EPC2 or EPC1 device can configure a device chain with multiple voltage levels. All 3.3-V and 2.5-V ACEX, APEX, APEX II, FLEX, and Mercury devices can be driven by higher-voltage signals. ...
Page 26
... The DATA, DCLK, and nCEO pins are used only to interface between the EPC2 configuration device and the APEX II, APEX 20K, Mercury, ACEX 1K, or FLEX 10K device it is configuring. The voltage tolerances of all EPC2 pins at 5.0 V and 3.3 V are listed in f For more information on APEX II, APEX 20K, Mercury, ACEX 1K, ...
Page 27
... EPC4, EPC8, EPC16, and EPC2 configuration devices can be programmed in-system through its industry-standard 4-pin JTAG interface. ISP capability in the EPC2, EPC4, EPC8, and EPC16 devices provides ease in prototyping and updating APEX II, APEX 20K, Mercury, ACEX 1K, or FLEX device functionality. The EPC8 and EPC16 devices can be programmed in-system via test equipment using SVF Files, Jam STAPL Files ( ...
Page 28
... IDCODE Selects the device IDCODE register and places it between TDI and TDO, allowing the device IDCODE to be serially shifted out of TDO. The device IDCODE for the EPC2 configuration device is shown below: 0000 0001000000000010 00001101110 1 USERCODE Selects the USERCODE register and places it between TDI and TDO, allowing the USERCODE to be serially shifted out of TDO ...
Page 29
... Operating Conditions Altera Corporation Configuration Devices for SRAM-Based LUT Devices Data Sheet Figure 10. EPC2 JTAG Waveforms TMS TDI t JCP t t JCH JCL TCK t JPZX TDO t JSSU Signal to Be Captured t JSZX Signal to Be Driven Table 11 shows the timing parameters and values for configuration devices. Table 11. JTAG Timing Parameters & ...
Page 30
... C –65 135 ° C 135 ° C Min Max Unit 4.75 (4.50) 5.25 (5.50) V 3.0 (3.0) 3.6 (3.6) V – ° C –40 85 ° Min Max Unit 2 0 (5) –0.3 0 – 0 0.4 V – – Altera Corporation ...
Page 31
... Numbers in parentheses are for industrial-temperature-range devices. (4) Maximum V rise time is 100 ms. CC (5) Certain EPC2 pins may be driven to 5.75 V when operated with a 3.3-V V (6) The I parameter refers to high-level TTL or CMOS output current; the I OH CMOS output current. (7) Capacitance is sample-tested only. ...
Page 32
... OE low to CLK disable delay OEC t OE low (reset) to nCASC delay NRCAS t OE low time (reset) minimum NRR Table 21. ACEX 1K, APEX 20K, APEX II, FLEX 10K & Mercury Device Configuration Parameters Using EPC2 Devices at 3.3-V Symbol Parameter t OE high to first clock delay high to data output enabled ...
Page 33
... CCA f CLK to data enable/disable CDOE t OE low to CLK disable delay OEC t OE low (reset) to nCASC delay NRCAS t OE low time (reset) minimum NRR Altera Corporation Configuration Devices for SRAM-Based LUT Devices Data Sheet Conditions Conditions Min Typ Max 200 ...
Page 34
... Table 2 to 1.8 V. Figures 4 and 6. Altera Corporation Unit MHz 100 ns ...
Page 35
... Notes: Altera Corporation Configuration Devices for SRAM-Based LUT Devices Data Sheet 35 ...
Page 36
... Configuration Devices for SRAM-Based LUT Devices Data Sheet ® 101 Innovation Drive Copyright © 2002 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the San Jose, CA 95134 stylized Altera logo, specific device designations, and all other words and logos that are identified as ...