EPC8XXX Altera Corporation, EPC8XXX Datasheet
EPC8XXX
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EPC8XXX Summary of contents
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... Altera Corporation August 2005 2. Enhanced Configuration Devices (EPC4, EPC8 & Enhanced configuration devices include EPC4, EPC8, and EPC16 devices Single-chip configuration solution for Stratix series, APEX™ II, APEX 20K (including APEX 20K, APEX 20KC, and APEX 20KE), Mercury™ ...
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... A configuration interface between the controller and the Altera FPGA(s) A JTAG interface on the controller that enables in-system programmability (ISP) of the flash memory An external flash interface that the controller shares with an external processor, or FPGA implementing a Nios (interface available after ISP and configuration) embedded processor ® Altera Corporation August 2005 ...
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... This page mode feature combined with the external flash interface allows remote and local updates of system configuration data. The enhanced configuration devices are compatible with the Stratix Remote System Configuration feature. Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet JTAG/ISP Interface ...
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... For more information on Stratix Remote System Configuration, refer to the Using Remote System Configuration with Stratix & Stratix GX Devices chapter of the Stratix Device Handbook. Real-time decompression of configuration data Programmable configuration clock (DCLK) Flash ISP Programmable power-on-reset delay (PORSEL) Altera Corporation August 2005 ...
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... The following sections briefly describe the different configuration schemes supported by the enhanced configuration device: FPP, PS, and concurrent configuration. Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet 2–5 Configuration Handbook, Volume 2 ...
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... Open-drain bidirectional configuration status nSTATUS signal, which is driven low by either device during POR and to signal an error during configuration. Low pulse on OE resets the enhanced configuration device controller. CONF_DONE Configuration done output signal driven by the FPGA. Description either directly or CC Altera Corporation August 2005 ...
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... For specific details on configuration interface connections including pull-up resistor values, supply voltages, and MSEL pin settings, refer to the appropriate FPGA family chapter in the Configuration Handbook. Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet Figure 2–2 shows the enhanced configuration device 2– ...
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... GND C-A0 (5) C-A1 (5) C-A15 (5) C-A16 (5) ® II software. To turn off the internal pull-up resistors, check the Disable nCS and Table 2–9. . Additionally, you must make the following pin connections in both CC WE#F RP#F N.C. N.C. N.C. CE# N.C. OE# N.C. V (1) CC VCCW (4) (4) (4) A0-F A1-F A15-F A16-F , TM0 to CC Altera Corporation August 2005 ...
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... Quartus II software and can be any number between 1 and 8. For example, three concurrent chains you can select the 4-bit PS mode, and connect the least Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet ...
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... PS mode using an enhanced configuration device. f For specific details on configuration interface connections including pull-up resistor values, supply voltages, and MSEL pin settings, refer to the appropriate FPGA family chapter in the Configuration Handbook. 2–10 Configuration Handbook, Volume 2 shows the schematic for configuring multiple FPGAs Altera Corporation August 2005 ...
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... PQFP and 88-pin Ultra FineLine BGA packages: C-RP# to F-RP#, C-WE# to F-WE#, TM1 to V GND, and WP (6) Connect the FPGA MSEL[] input pins to select the PS configuration mode. For details, refer to the appropriate FPGA family chapter in the Configuration Handbook. Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet V (1) V (1) ...
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... PS configuration modes supported Mode Name Mode ( Table 2–4: This is the number of valid DATA outputs for each configuration mode. Used Outputs Unused Outputs DATA[7..1] drive low DATA0 DATA[1..0] DATA[7..2] drive low DATA[3..0] DATA[7..4] drive low DATA[7..0] - Altera Corporation August 2005 ...
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... Micron MT28F400B3 for EPC4 devices) on the Altera web site at www.altera.com. Figure 2–4 interface being used. Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet The external flash interface signals cannot be shared between multiple enhanced configuration devices because this causes contention during in-system programming and configuration ...
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... CE# nINIT_CONF OE# DQ[15.. WP# VCCW GND BYTE# (3) TM1 PORSEL PGM[2..0] TMO EXCLK GND C-A0 (3) A0-F C-A1 (3) A1-F C-A15 (3) A15-F C-A16 (3) A16-F . Additionally, you must make the following pin connections in both CC Table 2–9. PLD or Processor WE# RP# A[20..0] RY/BY# CE# OE# DQ[15.. (4) (4) (4) , TM0 to CC Altera Corporation August 2005 ...
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... For example, if your system requires three configuration pages and includes two FPGAs, each page will store two SRAM Object Files (.sof) for a total of six SOFs in the configuration device. Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet The PGM[2 ...
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... MHz = 300 Mbps, reducing overall configuration time. You can enable the controller's decompression feature in the Quartus II software, Configuration Device Options window by turning on Compression Mode. 2–16 Configuration Handbook, Volume 2 Altera Corporation August 2005 ...
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... Logic Utilization Compression Ratio % Size Reduction Note to (1) Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet The decompression feature supported in the enhanced configuration devices is different from the decompression feature supported by the Stratix II FPGAs and the Cyclone series ...
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... The maximum DCLK input frequency supported by the FPGA is specified in the appropriate FPGA family chapter in the Configuration Handbook. 2–18 Configuration Handbook, Volume 2 Configuration Device Clock Divider Unit Divide MHz 33 MHz 50 MHz 66 MHz Internal Oscillator Figure 2–5 for a block DCLK Altera Corporation August 2005 ...
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... Enhanced configuration devices also support the ISP mode. The enhanced configuration device is compliant with the IEEE Std. 1532 draft 2.0 specification. Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet Min (MHz ...
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... Configuration Handbook, Volume 2 If initial programming of the enhanced configuration device is done in-system via the external flash interface, the controller must be kept in reset by driving the FPGA nCONFIG line low to prevent contention on the flash interface. Altera Corporation August 2005 ...
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... Output DCLK Input nCS nINIT_CONF Open-Drain Output Open-Drain OE Bidirectional Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet through 2–9 describe the enhanced configuration device pins. Description This is the configuration data output bus. DATA changes on each falling edge of DCLK ...
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... This flash input is not internally connected to the controller. Hence, an external loop back connection between C-RP# and F-RP# must be made on the board even when you are not using the external flash interface. When using the external flash interface, connect the external device to the RP# pin with the loop back. Altera Corporation August 2005 ...
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... You must connect the two pins at the board level (for example, on the printed circuit board (PCB), connect the C-WE# pin from controller to F-WE# pin from the flash memory). Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet ...
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... This pin must be connected to a valid logic level. For normal operation, this test pin must be connected to GND. For normal operating, this test pin must be connected not execute JTAG or ISP instructions until POR is complete ramp time and a CC Altera Corporation August 2005 ...
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... PORSEL is set to a high level and 100 ms when PORSEL is set to a low level. For more margin, the 100-ms setting can be selected to allow the FPGA to power-up before configuration is attempted. Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet ...
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... BST data to pass synchronously through a selected device to adjacent devices during normal device operation. (Table 2–10). Note (1) Altera Corporation August 2005 ...
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... Programming files (POF) can be converted to an Intel HEX format file (.hexout) using the Quartus II Convert Programming Files utility, for use with the programmers or processors. Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet Description allowing the device IDCODE to be serially shifted out to TDO ...
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... Ultra FineLine BGA 100-pin PQFP 100-pin PQFP 100-pin PQFP shows the timing requirements for the JTAG signals. JCP t t JCL JPSU t JPCO t t JSSU JSH t JSCO Table 2–11 Adapter PLMUEPC-88 PLMQEPC-100 PLMQEPC-100 PLMQEPC-100 t JPH t JPXZ t JSXZ Altera Corporation August 2005 ...
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... Update register clock to output JSCO t Update register high-impedance to valid output JSZX t Update register valid output to high impedance JSXZ Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet shows the timing parameters and values for the enhanced Parameter Min Max Unit ...
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... HC LC bit/byte bit/byte Tri-State defines the timing parameters when using the enhanced Condition 40% duty cycle 40% duty cycle 40% duty cycle (1) (2) User Mode Min Typ Max Unit 66.7 MHz (1) ns 277 ns 277 ns Altera Corporation August 2005 ...
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... OUT P Power dissipation D T Storage temperature STG T Ambient temperature AMB T Junction temperature J Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet Condition 40% duty cycle 40% duty cycle 40% duty cycle 133 MHz 133 MHz 2 ms 100 ms = 0.5 (DCLK period) - 2.5 ns. OH through 2– ...
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... Internal pull up (OE, nCS, nINIT, CONF) Supply Current Values CC Condition Min Typ 50 60mA (1) Max Unit 3 0 Typ Max Unit 3.3 3 0.3 0 0.45 V 0.2 V μA 10 μ kΩ Max Unit μA 100 μA 90mA (1) Altera Corporation August 2005 ...
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... PQFP package. Enhanced configuration devices support vertical migration in the 100-pin PQFP package. Figure 2–8 package. The Gerber file for this layout is on the Altera web site. Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet Condition Min ...
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... A17 CE# GND Figure 2–9 DCLK GND DATA7 NC DQ14 DQ7 DATA5 DATA6 DQ4 DQ5 DATA4 VCC VCC DATA3 DQ2 DQ3 DATA2 DQ0 DQ1 DATA1 A1 VCC GND DATA0 OE# TM0 GND NC shows the 100-pin PQFP PCB Altera Corporation August 2005 ...
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... Used 0.5-mm increase for front and back of nominal foot length (2) Used 0.3-mm increase to maximum foot width. f For package outline drawings, refer to the Altera Device Package Information Data Sheet. Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet 25.3 mm 0.65-mm pad pitch 19.3 mm 0.410 mm 2– ...
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... PQFP EPC4 100-pin PQFP EPC8 100-pin PQFP EPC8 100-pin PQFP EPC16 100-pin PQFP EPC16 100-pin PQFP EPC16 88-pin UBGA Temperature Ordering Code Commercial EPC4QC100 Industrial EPC4QI100 Commercial EPC8QC100 Industrial EPC8QI100 Commercial EPC16QC100 Industrial EPC16QI100 Commercial EPC16UC88 Altera Corporation August 2005 ...