LFXP15 Lattice Semiconductor, LFXP15 Datasheet - Page 27

• Manufacturer Part Number: LFXP15
• Description: LatticeXP Family
• Manufacturer: Lattice Semiconductor

Lattice Semiconductor
Typical I/O Behavior During Power-up
The internal power-on-reset (POR) signal is deactivated when V
After the POR signal is deactivated, the FPGA core logic becomes active. It is the user’s responsibility to ensure
that all other V
I/O banks that are critical to the application. The default configuration of the I/O pins in a blank device is tri-state
with a weak pull-up to VCCIO. The I/O pins will not take on the user configuration until VCC, VCCAUX and VCCIO
have reached satisfactory levels at which time the I/Os will take on the user-configured settings.
The V
ers. In order to simplify system design while providing consistent and predictable I/O behavior, it is recommended
that the I/O buffers be powered-up prior to the FPGA core fabric. V
together with the V
Supported Standards
The LatticeXP sysIO buffer supports both single-ended and differential standards. Single-ended standards can be
further subdivided into LVCMOS, LVTTL and other standards. The buffers support the LVTTL, LVCMOS 1.2, 1.5,
1.8, 2.5 and 3.3V standards. In the LVCMOS and LVTTL modes, the buffer has individually configurable options for
drive strength, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch) and open drain. Other sin-
gle-ended standards supported include SSTL and HSTL. Differential standards supported include LVDS, BLVDS,
LVPECL, differential SSTL and differential HSTL. Tables 2-7 and 2-8 show the I/O standards (together with their
supply and reference voltages) supported by the LatticeXP devices. For further information on utilizing the sysIO
buffer to support a variety of standards please see the details of additional technical documentation at the end of
this data sheet.
Table 2-7. Supported Input Standards
CC
and V
Single Ended Interfaces
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI
HSTL18 Class I, II
HSTL18 Class III
HSTL15 Class I
HSTL15 Class III
SSTL3 Class I, II
SSTL2 Class I, II
SSTL18 Class I
Differential Interfaces
Differential SSTL18 Class I
Differential SSTL2 Class I, II
Differential SSTL3 Class I, II
Differential HSTL15 Class I, III
Differential HSTL18 Class I, II, III
LVDS, LVPECL
BLVDS
1. When not specified V
2. JTAG inputs do not have a fixed threshold option and always follow V
CCIO
CCAUX
CC
banks are active with valid input logic levels to properly control the output logic states of all the
Input Standard
supply the power to the FPGA core fabric, whereas the V
and V
2
2
2
CCAUX
CCIO
supplies.
can be set anywhere in the valid operating range.
V
REF
2-24
1.08
0.75
1.25
0.9
0.9
1.5
0.9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(Nom.)
CC
CCIO
and V
CCJ.
supplies should be powered up before or
CCAUX
LatticeXP Family Data Sheet
CCIO
V
have reached satisfactory levels.
CCIO
supplies power to the I/O buff-
1.8
1.5
3.3
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(Nom.)
www.DataSheet4U.com
Architecture