nRF24E2 Nordic VLSI, nRF24E2 Datasheet - Page 16

• Manufacturer Part Number: nRF24E2
• Description: Single Chip RF Transmitter + MCU + ADC NRF2402 2.4GHz RF Transmitter
• Manufacturer: Nordic VLSI

PRODUCT SPECIFICATION
P1 may also be configured as a SPI master port , and is then controlled by the 3 SFR
registers 0xB2, 0xB3, 0xB4 as shown in the table below.
Table 3-6 : SPI control and data SFR-registers
Whenever SPI_DATA register is written to, a sequence of 8 pulses is started on
SCK, and the 8 bits of SPI_DATA register are clocked out on SDO with msb first.
Simultaneously 8 bits from SDI are clocked into SPI_DATA register. Ouput data is
shifted on negedge SCK, and input data is read on posedge SCK. This is illustrated in
Figure 3-1 : SPI interface timing. When the 8 bits are done, SPI_READY interrupt
(EXIF.5) goes active, and the 8 bits from SDI may be read from SPI_DATA register.
The EXIF.5 bit must be cleared before starting another SPI transaction by writing to
SPI_DATA register again.
SCK, SDO and SDI may be external pins or internal signals, as defined in SPI_CTRL
register.
Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone [phone] - Fax [phone]
Revision: 1.0
B2
B3
B4
R/W
R/W
R/W
8
2
2
0
0
0
SPI_DATA SPI data input/output
SPI_CTRL
SPICLK
Qhtrà %ÂsÃ(
00 -> SPI not used no clock generated
Divider factor from CPU clock to SPI clock
01 -> SPI connected to port P1 (as for booting)
10 -> SPI connected to RADIO
11 -> reserved, do not use
00: 1/8
01: 1/16 of CPU clock frequency
10: 1/32 of CPU clock frequency
11: 1/64 of CPU clock frequency
The CPU clock is the oscillator generated clock
described in Crystal Specification page 85
(see Table 4-2 : RADIO register )
another GPIO must be used as chip select
(see also Table 3-4 : Port 1 (P1) functions)
transmitter for TX or for configuration
of CPU clock frequency
August 2003