STK16C88 Simtek, STK16C88 Datasheet - Page 7

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STK16C88

Manufacturer Part Number
STK16C88
Description
CMOS Nonvolatile Static RAM
Manufacturer
Simtek
Datasheet

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The AutoStorePlus™ STK16C88 is a fast 32K x 8
SRAM that does not lose its data on power-down.
The data is preserved in integral QuantumTrap™
EEPROM
ity of the STK16C88 does not require any system
intervention or support: AutoStorePlus™ on power-
down and automatic RECALL on power-up guaran-
tee data integrity without the use of batteries
NOISE CONSIDERATIONS
Note that the STK16C88 is a high-speed memory
and so must have a high-frequency bypass capaci-
tor of approximately 0.1 F connected between V
and V
possible. As with all high-speed
careful routing of power, ground and signals will
help prevent noise problems.
SRAM READ
The STK16C88 performs a
and G are low and W is high. The address specified
on pins A
bytes will be accessed. When the
by an address transition, the outputs will be valid
after a delay of t
initiated by E or G, the outputs will be valid at t
at t
outputs will repeatedly respond to address changes
within the t
sitions on any control input pins, and will remain valid
until another address change or until E or G is
brought high.
SRAM WRITE
A
low. The address inputs must be stable prior to
entering the
until either E or W goes high at the end of the cycle.
The data on the common I/O pins DQ
ten into the memory if it is valid t
of a W controlled
E controlled
It is recommended that G be kept high during the
entire
the common I/O lines. If G is left low, internal circuitry
will turn off the output buffers t
February 2002
WRITE
GLQV
SS
WRITE
, whichever is later (
, using leads and traces that are as short as
while power is unavailable. The nonvolatil-
cycle is performed whenever E and W are
0-14
AVQV
WRITE
WRITE
determines which of the 32,768 data
cycle to avoid data bus contention on
access time without the need for tran-
AVQV
WRITE
.
(
cycle and must remain stable
READ
or t
READ
READ
cycle #1). If the
DVEH
WLQZ
before the end of an
cycle #2). The data
DVWH
CMOS
cycle whenever E
after W goes low.
READ
DEVICE OPERATION
before the end
0-7
ICs, normal
will be writ-
is initiated
READ
ELQV
or
CC
is
5-71
AutoStorePlus™ OPERATION
The STK16C88’s automatic
is completely transparent to the system. The
AutoStore™ initiation takes less than 500ns when
power is lost (V
depends only on its internal capacitor for
completion. This safe transfer of data from
EEPROM
slew rate.
In order to prevent unneeded
automatic
one
most recent
initiated
whether or not a
POWER-UP RECALL
During power up, or after any low-power condition
(V
latched. When V
voltage of V
be initiated and will take t
If the STK16C88 is in a
power-up
To help avoid this situation, a 10k
be connected either between W and system V
between E and system V
SOFTWARE NONVOLATILE STORE
The STK16C88 software
executing sequential
address locations. During the
of the previous nonvolatile data is first performed,
followed by a program of the nonvolatile elements.
The program operation copies the
nonvolatile memory. Once a
ated, further input and output are disabled until the
cycle is completed.
Because a sequence of
addresses is used for
tant that no other
vene in the sequence or the sequence will be
aborted and no
To initiate the software
READ
CC
WRITE
< V
sequence must be performed:
STORE
RESET
takes place regardless of power supply
RECALL
STORE
SWITCH
operation has taken place since the
), an internal
STORE
STORE
CC
cycles are performed regardless of
WRITE
, a
CC
s will be ignored unless at least
, the
< V
READ
once again exceeds the sense
RECALL
READ
SWITCH
or
SRAM
STORE
or
operation has taken place.
STORE
CC
RESTORE
WRITE
STORE
RECALL
or
RECALL
.
) at which point the part
RECALL
cycles from six specific
STORE
WRITE
cycle will automatically
READ
data will be corrupted.
STORE
STORE
initiation, it is impor-
to complete.
cycle, the following
STORE
state at the end of
cycle is initiated by
will take place.
s from specific
cycle. Software-
SRAM
on power-down
accesses inter-
request will be
STK16C88
resistor should
cycle an erase
cycle is initi-
operations,
data into
SRAM
STORE
CC
or
to

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