SMT4214 Summit Microelectronics, Inc., SMT4214 Datasheet
SMT4214
Available stocks
Related parts for SMT4214
SMT4214 Summary of contents
Page 1
... The above drawing illustrates the use of the SMT4214 in a multi-device application. It should be noted this is just an example and the specific component values are purposely not shown. Note 1 - Several pins have internal resistors so external resistors are optional (see the Internal Functional Block Diagram). If external resistors are used they should be tied to VDD_CAP on the Master. © ...
Page 2
... Each supply on the card is assigned its own manager on the SMT4214. If there are more than four supplies, the SMT4214 can be linked with other SMT4214’s through the use of the PWR_ON#, LINK#, VRLINK and FS# pins. ...
Page 3
... SEATED Once the power-on operation is initiated the SMT4214 will wait until all of the VI’s for the designated soft start channels have reached their programmed thresholds. At this point the VGATE outputs of the soft start channels will ramp up and turn on their corresponding card-side voltages ...
Page 4
... I FS I/O, therefore, all FS# pins in a multi- device application must be tied together. One or more of the SMT4214’s could be configured to generate a force shutdown if an under-voltage condition is detected. When a device is configured as a master its VRLINK pin will be configured as an output; all other devices in the system are slaves ...
Page 5
... INTERNAL FUNCTIONAL BLOCK DIAGRAM Summit Microelectronics, Inc 2061 1.0 8/16/02 SMT4214 Preliminary Information 5 ...
Page 6
... If FS# is brought low, the SMT4214 will immediately take the VGATE outputs to 0V. If multiple SMT4214’s are used on a single board, the FS# outputs can be tied together. In this configuration it is possible for a fault condition on one SMT4214 to shutdown all of the SMT4214’ ...
Page 7
... SMT4214 is designated as the master its VRLINK will become an output providing the ramp reference of the card-side voltages for the slave SMT4214’s. If the SMT4214 is designated as a slave its VRLINK will become the input for the VRLINK of the master. Link is an active low open-drain I/O internally connected to VDD_CAP through a 100kΩ ...
Page 8
... Option 2 (MOSFETs on 2mA SINK MOSFET switches enabled Allowable differential between VO pins programmed for tracking 5.0V Open Drain Outputs, I See Pin Descriptions 2061 1.0 8/16/02 SMT4214 Preliminary Information ° be equal to or greater than 2.7V (voltage level measured on pin 16). Min. Typ. 2.7 0.9 180 200 ...
Page 9
... PRTO t = 200ms PRTO t = OFF UVFILT t = 0.2ms UVFILT t = 1.6ms UVFILT t = 12.8ms UVFILT t = 25ms SEATED t = 200ms PWRON VGG_CAP fully charged VGATE Capacitance = 10nF t SEATED 2061 1.0 8/16/02 SMT4214 Preliminary Information Min. Typ. Max. Unit -25 t +25 % PRTO -25 t +25 % UVFILT -25 t +25 % SEATED -25 t +25 % PWRON 1 µs 1 µs ...
Page 10
... Note 1/ Note 1/ Noise suppression VGG_CAP Capacitor =1uF, VGG_CAP=10. HIG HD:DAT SU:DAT HD:SDA Figure 6 . Basic I C Serial Interface Timing 2061 1.0 8/16/02 SMT4214 Preliminary Information Min Typ Max 0 100 4.7 4.0 4.7 4.7 4.0 4.7 0.2 3.5 0.2 1000 300 250 0 100 100 (For W rite O peration O nly) ...
Page 11
... Ground Figure 7A – SMX3200 Programmer and I SMT4214, the PWR_ON# pin must be high in order to program the device. It can be done optionally through the SMX3200 programmer and R1/R2 or through an external control signal or switch. The SMX3200 should be disconnected after programming the part. If the PWR_ON# is hardwired to ground, this method will not work ...
Page 12
... DEVELOPMENT HARDWARE & SOFTWARE (Cont.) Com m on Ground Figure 7B – An alternative connection between the SMX3200 Programmer and SMT4214 I connections. Although this alternative requires additional components, it will work regardless of the position of the external PWR_ON# control signal or switch (S1). The zener diode (D3) provides further protection by clamping the output voltage at 5 ...
Page 13
... APPLICATIONS INFORMATION (Cont.) Figure 8A – Example application using two SMT4214s connected in a Master/Slave configuration. The Master is shown above, the Slave is shown in Figure 8B. Summit Microelectronics, Inc 2061 1.0 8/16/02 SMT4214 Preliminary Information 13 ...
Page 14
... APPLICATIONS INFORMATION (cont.) Figure 8B – Example application using two SMT4214s connected in a Master/Slave configuration. The Slave is shown above, the Master is shown in Figure 8A Summit Microelectronics, Inc 2061 1.0 8/16/02 SMT4214 Preliminary Information 14 ...
Page 15
... DEFAULT CONFIGURATION REGISTER SETTINGS – SMT4214G-115 Register Hex Contents R00 B4 R01 69 R02 41 R03 28 R04 F1 R05 21 R06 00 Application Note 28 contains a complete description of the Windows GUI and the default settings of each of the 6 individual Configuration Registers. Summit Microelectronics, Inc Channel A UV Trip Point = 4.5V Channel B UV Trip Point = 3.0V Channel C UV Trip Point = 2 ...
Page 16
... PACKAGE Summit Microelectronics, Inc 28 Lead SSOP Package 2061 1.0 8/16/02 SMT4214 Preliminary Information 16 ...
Page 17
... SM T4214G xx AYYW W NOTICE Please check the Summit Microelectronics Inc. web site at Power Management for Communications™ 2061 1.0 8/16/02 SMT4214 Preliminary Information Sum m it Part Status Tracking Code (Blank, MS, ES, 01, 02,...) (Sum m it Use) Date Code (YYW W ) Lot tracking code (Sum m it use) ...