WM8753 Wolfson Microelectronics plc, WM8753 Datasheet - Page 51
WM8753
Manufacturer Part Number
WM8753
Description
HI FI AND TELEPHONY DUAL CODEC
Manufacturer
Wolfson Microelectronics plc
Datasheet
1.WM8753.pdf
(87 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
WM8753
Manufacturer:
WM
Quantity:
20 000
Part Number:
WM8753G
Manufacturer:
WM
Quantity:
20 000
Company:
Part Number:
WM8753LGEB
Manufacturer:
TOSHIBA
Quantity:
3 000
Part Number:
WM8753LGEB/RV
Manufacturer:
WOLFSON
Quantity:
20 000
Part Number:
WM8753LGEFL/RV
Manufacturer:
WOLFSON
Quantity:
20 000
WM8753L
GENERAL PURPOSE INPUT/OUTPUT
w
The WM8753L has four dual purpose input/output pins.
Pin 44 (MODE/GPIO3) is sampled on powerup to determine the control interface mode (2-wire or 3-
wire) of the WM8753L. After powerup pin 43 may be used as a GPIO, its use configurable using
GPIO3M[2:0].
Pin 45 (CSB/GPIO5) is also sampled on powerup. If 2-wire interface control mode is the value on pin
45 on powerup is used to select the 2-wire address. After powerup, if 2-wire mode is selected, pin 44
may be used as a GPIO, its use configurable using GPIO5M[1:0]. If 3-wire control interface mode is
selected pin 44 is always configured as an input and is used as the 3-wire interface latch signal.
Pin 43 (GPIO4) is a dedicated GPIO pin with TTL compatible input thresholds and CMOS output
thresholds relative to DBVDD, making it ideal for headphone detection. It also features an optional
pull-up/pull-down resistor. GPIO4M[2:0] is used to configure the GPIO4 pin.
Pins 13 and 14 (GP1/CLK1 and GP2/CLK2) are general purpose outputs and may be configured to
either output the PLL clock outputs or may be used as general purpose outputs. They are configured
using GP1M[2:0] and GP2M[2:0].
In 3-wire interface mode pin GPIO5/CSB cannot be used as a GPIO as it is used to latch the data.
Setting GPIO5M to 01, 10 or 11 will prevent the device from being written to in 3-wire mode.
GP2/CLK2 may be configured to output a clock at 256 x the ADC or Hi-Fi DAC sample rate frequency
(fs), e.g. if DAC sample rate is set to 8kHz (SR = 00110) output clock will be 256 x 8kHz =
2.048MHz.
selection input.
select input.
GP1/CLK1: General purpose output 1, or PLL1 clock output.
GP2/CLK2: General purpose output 2, or PLL2 clock output.
GPIO3: General purpose input/output 3 and control interface mode
GPIO4: General purpose input/output 4, or head phone detection input.
GPIO5: General purpose input/output 5 and control interface chip/address
AI Rev 3.1 June 2004
Advanced Information
51