AD823A Analog Devices, AD823A Datasheet - Page 12

• Manufacturer Part Number: AD823A
• Description: Dual, 16 Mhz, Rail-to-rail Fet Input Amplifier
• Manufacturer: Analog Devices

AD823
The first pole in the denominator is the dominant pole of the
amplifier, and occurs at about 18 Hz. This equals the input
stage output impedance R1 multiplied by the Miller-multiplied
value of C1. The second pole occurs at the unity-gain band-
width of the output stage, which is 23 MHz. This type of archi-
tecture allows more open loop gain and output drive to be
obtained than a standard two-stage architecture would allow.
OUTPUT IMPEDANCE
The low frequency open loop output impedance of the
common-emitter output stage used in this design is approxi-
mately 30 k . While this is significantly higher than a typical
emitter follower output stage, when connected with feedback
the output impedance is reduced by the open loop gain of the
op amp. With 109 dB of open loop gain the output impedance
is reduced to less than 0.2 . At higher frequencies the output
impedance will rise as the open loop gain of the op amp drops;
however, the output also becomes capacitive due to the integra-
tor capacitors C1 and C2. This prevents the output impedance
from ever becoming excessively high (see Figure 17), which can
cause stability problems when driving capacitive loads. In fact,
the AD823 has excellent cap-load drive capability for a high fre-
quency op amp. Figure 33 shows the AD823 connected as a fol-
lower while driving 470 pF direct capacitive load. Under these
conditions the phase margin is approximately 20 . If greater
phase margin is desired a small resistor can be used in series
with the output to decouple the effect of the load capacitance
from the op amp (see Figure 25). In addition, running the part
at higher gains will also improve the capacitive load drive capa-
bility of the op amp.
g
g
Figure 36. Small Signal Schematic
m
m
VI
VI
R1
R1
S1P
S1N
C5
C1
g
m2
R2
C2
V
OUT
–12–
APPLICATION NOTES
INPUT CHARACTERISTICS
In the AD823, n-channel JFETs are used to provide a low
offset, low noise, high impedance input stage. Minimum input
common-mode voltage extends from 0.2 V below –V
less than +V
rail will cause a loss of amplifier bandwidth and increased
common-mode voltage error.
The AD823 does not exhibit phase reversal for input voltages
up to and including +V
AD823 voltage follower to a 0 V to +5 V (+V
input. The input and output are superimposed. The output
polarity tracks the input polarity up to +V
The reduced bandwidth above a 4 V input causes the rounding
of the output wave form. For input voltages greater than +V
resistor in series with the AD823’s plus input will prevent phase
reversal, at the expense of greater input voltage noise. This is il-
lustrated in Figure 37b.
b. V
IN
= 0 to +V
a. Response with R
GND
+V
GND
S
S
. Driving the input voltage closer to the positive
V
Figure 37. AD823 Input Response
IN
100
90
0%
10
100
90
10
0%
S
+ 200 mV; V
1V
1V
1V
1V
S
R
. Figure 37a shows the response of an
P
1V
AD823
P
+5V
= 0; V
OUT
= 0 to +V
IN
from 0 to V
S
10µs
—no phase reversal.
2 s
S
) square wave
S
; R
P
S
V
= 49.9 k
S
OUT
to 1 V
REV. 0
S
, a