EK43503-01 Peregrine Semiconductor Corp., EK43503-01 Datasheet
EK43503-01
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EK43503-01 Summary of contents
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... V or 5.0 V Power Supply Voltage Fast switch settling time Programming Modes: High-attenuation state @ power-up (PUP) CMOS Compatible No DC blocking capacitors required Packaged in a 24-lead 4x4x0.85 mm QFN RF Output A2 P/S ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Excellent low-frequency performance Direct Parallel Latched Parallel Serial Page ...
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... Frequency (GHz) ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 3 5 Frequency 9 kHz ≤ 6 GHz 9 kHz ≤ 4 GHz 4 GHz ≤ 6 GHz 4 GHz ≤ 6 GHz 4 GHz ≤ 6 GHz 9 kHz ≤ 6 GHz 20 MHz - 6 GHz 20 MHz – 6 GHz DC ≤ ...
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... Frequency (GHz) 0dB 1dB 2dB 8dB 16dB 31dB 500 1000 1500 2000 2500 Frequency (MHz) ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. 1dB 2dB 16dB 31dB 4dB 4dB 3000 3500 4000 4500 Page ...
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... Switching rate is defined to be the speed at which the DSA can be toggled across attenuation states. Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOS™ devices are immune to latch-up. ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page Table 3. Operating Ranges V Power Supply Voltage ...
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... Document No. 70-0252-05 │ www.psemi.com Function Table 8. Attenuation Word Truth Table LSB (first in ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Attenuation Word (LSB ...
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... Latch Enable (LE). The SI and CLK inputs allow data to be serially entered into the shift register. Serial data is clocked in LSB first. ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page The shift register must be loaded while LE is held LOW to prevent the attenuator value from changing as data is entered ...
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... T 100 - ns 100 - ns 100 - ns 100 - ns 100 - ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. T DIH T PSIH T LESU T LEPW T PD VALID Characteristics < 85° C, unless otherwise specified A Parameter Min Latch Enable minimum LEPW pulse width Parallel data setup time DISU T Parallel data hold time ...
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... Parallel is selected in the software. For manual latched-parallel programming, the procedure is identical to direct-parallel except now the LE pin on the Serial header must be logic low ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page Figure 17. Evaluation Board Layout Peregrine Specification 101-0310 Note: Reference Figure 18 for Evaluation Board Schematic as the parallel bits are applied ...
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... DSA 50 Ohm 4x4 MLP24 5 RF1 J4 6 GND Z=50 Ohm SMA 1 Note: Capacitors C1-C8, C13, & C14 may be omitted. SERIAL HEADER 4 CLK 1 CLOCK DATA 2 DATA GND CLK GND J5 14 RF2 SMA 13 1 GND Z=50 Ohm ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page ...
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... K = 1.1 0 YYWW = Date Code ZZZZZ = Last five digits of Lot Number Description PE43503 – 24QFN 4x4mm-EK PE43503 G - 24QFN 4x4mm-75A ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Pin 1 Top of Device Device Orientation in Tape Package Shipping Method Evaluation Kit Green 24-lead 4x4mm QFN Bulk or tape cut from reel Green 24-lead 4x4mm QFN 3000 units / T& ...
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... The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a CNF (Customer Notification Form). ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page Peregrine Semiconductor, Asia Pacific (APAC) Shanghai, 200040, P.R. China ...