AT91SAM9260 ATMEL Corporation, AT91SAM9260 Datasheet - Page 15

• Manufacturer Part Number: AT91SAM9260
• Description: AT91 ARM Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

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6. I/O Line Considerations
6.1
6.2
6.3
6.4
6221DS–ATARM–22-Sep-06
JTAG Port Pins
Test Pin
Reset Pins
PIO Controllers
plied to the pins is 1.8V only. The user must program the EBI voltage range before getting the
device out of its Slow Clock Mode.
TMS, TDI and TCK are Schmitt trigger inputs and have no pull-up resistors.
TDO and RTCK are outputs, driven at up to VDDIOP0, and have no pull-up resistors.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level
(tied to VDDBU). It integrates a permanent pull-down resistor of about 15 k to GNDBU, so
that it can be left unconnected for normal operations.
The NTRST signal is described in
All the JTAG signals are supplied with VDDIOP0.
The TST pin is used for manufacturing test purposes when asserted high. It integrates a per-
manent pull-down resistor of about 15 k to GNDBU, so that it can be left unconnected for
normal operations. Driving this line at a high level leads to unpredictable results.
This pin is supplied with VDDBU.
NRST is a bidirectional with an open-drain output integrating a non-programmable pull-up
resistor. It can be driven with voltage at up to VDDIOP0.
NTRST is an input which allows reset of the JTAG Test Access port. It has no action on the
processor.
As the product integrates power-on reset cells, which manages the processor and the JTAG
reset, the NRST and NTRST pins can be left unconnected.
The NRST and NTRST pins both integrate a permanent pull-up resistor to VDDIOP0. Its value
can be found in the table “DC Characteristics” in the section “AT91SAM9260 Electrical Char-
acteristics” in the product datasheet.
The NRST signal is inserted in the Boundary Scan.
All the I/O lines are managed by the PIO Controllers integrate a programmable pull-up resistor
of 100 k typical. Programming of this pull-up resistor is performed independently for each I/O
line through the PIO Controllers.
After reset, all the I/O lines default as inputs with pull-up resistors enabled, except those which
are multiplexed with the External Bus Interface signals and that must be enabled as Peripheral
at reset. This is explicitly indicated in the column “Reset State” of the PIO Controller multiplex-
ing tables.
Section
6.3.
AT91SAM9260 Preliminary
15