LinkZero-LP Power Integrations, Inc., LinkZero-LP Datasheet - Page 6

• Manufacturer Part Number: LinkZero-LP
• Description: LinkZero-LP, an upgrade to PI's popular LinkSwitch-LP, incorporates new technology which enables the device to automatically enter into and wake up from no-load mode while disipating less than 5 mW - substantially less than the IEC definition of zero
• Manufacturer: Power Integrations, Inc.

Figure 5.
Rev. B 12/07/10
Thermal Considerations
The copper area underneath the LinkZero-LP (U1) acts not only
as a single point ground, but also as a heatsink. As it is
connected to the quiet source node, this area should be
maximized for good heat sinking of U1. The same applies to
the cathode of the output diode.
Y Capacitor
The placement of the Y-type capacitor (if used) should be
directly from the primary input filter capacitor positive terminal to
the common/return terminal of the transformer secondary.
Such a placement will route high magnitude common-mode
surge currents away from U1. Note: If an input π EMI filter is
used, the inductor in the π filter should be placed between the
negative terminals on the input filter capacitors.
Output Diode (D
For best performance, the area of the loop connecting the
secondary winding, the output diode (D
capacitor (C
copper area should be provided at the anode and cathode
terminals of the diode for heat sinking. A larger area is preferred
at the electrically “quiet” cathode terminal. A large anode area
can increase high frequency conducted and radiated EMI.
Resistor R
Quick Design Checklist
As with any power supply design, all LinkZero-LP designs
should be verified on the bench to make sure that component
specifications are not exceeded under worst-case conditions.
6
PCB Layout of a 2.1 W, 6 V, 350 mA Charger.
S
D
and C
O
)should be minimized. In addition, sufficient
BP
C
LNK574
FB
R
U1
FB2
O
S
)
represent the secondary side RC snubber.
R
BP
–
HV DC
IN
+
C
BP
O
) and the output filter
C
B
R
FB1
D
B
Transformer
The following minimum set of tests is strongly recommended:
1. Maximum drain voltage – Verify that V
2. Maximum drain current – At maximum ambient temperature,
3. Thermal check – At specified maximum output power,
4. Negative drain voltages – clampless designs may allow the
T1
660 V at the highest input voltage and peak (overload) output
power. This margin to the 700 V BV
margin for design variation, especially in clampless designs.
maximum input voltage and peak output (overload) power,
verify drain current waveforms for any signs of transformer
saturation and excessive leading-edge current spikes at
startup. Repeat under steady state conditions and verify that
the leading-edge current spike event is below I
end of the t
current should be below the specified absolute maximum
ratings.
minimum input voltage and maximum ambient temperature,
verify that the temperature specifications are not exceeded
for LinkZero-LP, transformer, output diode and output
capacitors. Enough thermal margin should be allowed for
part-to-part variation of the R
fied in the data sheet. Under low line and maximum power,
maximum LinkZero-LP source pin temperature of 100 °C is
recommended to allow for these variations.
drain voltage to ring below source and cause reverse
currents to flow from source to drain. Verify that any such
current remains within the envelope shown in Figure 9.
LEB(MIN)
. Under all conditions, the maximum drain
R
S
DS(ON)
–
LV DC
OUT
of LinkZero-LP as speci-
DSS
+
DS
J3
specification gives
does not exceed
C
R6
S
www.powerint.com
LIMIT(MIN)
C
D
PI-6098-092410
O
O
at the