MT9122 Zarlink Semiconductor, MT9122 Datasheet - Page 10

• Manufacturer Part Number: MT9122
• Description: Dual Voice Echo CANceller (ITU-T G165 Compliant) With Disable Tone Detection
• Manufacturer: Zarlink Semiconductor

MT9122
device determines the mode of operation by
monitoring the signal applied to the F0i pin. When a
valid ST-BUS frame pulse is applied to the F0i pin,
the MT9122 will assume ST-BUS operation. If F0i is
tied continuously to Vss the MT9122 will assume SSI
operation.
ST-BUS Operation
The ST-BUS PCM interface conforms to Zarlink’s
ST-BUS standard and it is used to transport 8 bit
companded PCM data (using one timeslot) or 16 bit
2’s complement linear PCM data (using two
timeslots). Pins ENA1 and ENB1 select timeslots on
PORT1 while pins ENA2 and ENB2 select timeslots
on PORT2. See Table 4 and Figures 5 to 8.
Note that if the device is in back-to-back or extended
delay configurations, the second timeslot in any ST-
BUS Mode contains undefined data. This means that
the following timeslots contain undefined data:
timeslot 1 in ST-BUS Mode 1; timeslot 3 in ST-BUS
Modes 2 & 3 and timeslots 2 and 3 in ST-BUS Mode
4.
SSI Operation
The SSI PCM interface consists of data input pins
(Rin, Sin), data output pins (Sout, Rout), a variable
rate bit clock (BCLK), and four enable pins
(ENA1,ENB1, ENA2 and ENB2) to provide strobes
for data transfers. The active high enable may be
either 8 or 16 BCLK cycles in duration. Automatic
detection of the data type (8 bit companded or 16 bit
2’s complement linear) is accomplished internally.
The data type cannot change dynamically from one
frame to the next.
10
ENB1 ENA1
Rin/Sout
Enable Pins
PORT1
0
0
1
1
0
1
0
1
Mode 1. 8 bit companded PCM I/O on
timeslots 0 & 1.
Mode 2. 8 bit companded PCM I/O on
timeslots 2 & 3.
Mode 3. 8 bit companded PCM I/O on
timeslots 2 & 3. Includes D & C chan-
nel bypass in timeslots 0 & 1.
Mode 4. 16 bit 2’s complement linear
PCM I/O on timeslots 0 - 3.
Table 4 - ST-BUS Mode Select
ST-BUS Mode
Selection
ENB2
Sin/Rout
Enable Pins
PORT2
0
0
1
1
ENA2
0
1
0
1
In SSI operation, the frame boundary is determined
by the rising edge of the ENA1 enable strobe (see
Figure 9). The other enable strobes (ENB1, ENA2
and ENB2) are used for parsing input/output data
and they must pulse within 125 microseconds of the
rising edge of ENA1. If they are unused, they must
be tied to Vss.
In SSI operation, the enable strobes may be a mixed
combination of 8 or 16 BCLK cycles allowing the
flexibility to mix 2’s complement linear data on one
port (e.g., Rin/Sout) with companded data on the
other port (e.g., Sin/Rout).
PCM Law and Format Control (LAW, FORMAT)
The PCM companding/coding law used by the
MT9122 is controlled through the LAW and FORMAT
pins. ITU-T G.711 companding curves for µ-Law and
A-Law are selected by the LAW pin. PCM coding
ITU-T G.711 and Sign-Magnitude are selected by the
FORMAT pin. See Table 6.
Linear PCM
The 16-bit 2’s complement PCM linear coding
permits a dynamic range beyond that which is
specified in ITU-T G.711 for companded PCM. The
echo-cancellation algorithm will accept 16 bits 2’s
complement linear code which gives a dynamic
range of +15dBm0. Note however that the tone
Enable Strobe Pin
PCM Code
+ Full Scale
- Full Scale
+ Zero
- Zero
ENA1
ENB1
ENA2
ENB2
Table 5 - SSI Enable Strobe Pins
Table 6 - Companded PCM
Sign-Magnitude
LAW = 0 or 1
FORMAT=0
1111 1111
1000 0000
0000 0000
0111 1111
µ/A-LAW
Echo Canceller
A
B
A
B
1000 0000
1111 1111
0111 1111
0000 0000
LAW = 0
µ-LAW
ITU-T (G.711)
FORMAT=1
Data Sheet
1010 1010
1101 0101
0101 0101
0010 1010
LAW =1
A-LAW
Port
1
1
2
2