MT9315 Zarlink Semiconductor, MT9315 Datasheet - Page 22

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MT9315

Manufacturer Part Number
MT9315
Description
Acoustic Echo CANceller
Manufacturer
Zarlink Semiconductor
Datasheet
Advance Information
Reset 00h
Reset 00h
Reset 00h
Power Up
Power Up
Power Up
36h Read
37h Read
38h Read
Address:
Address:
Address:
SIPD
SIPD
SIPD
SIPD
SIPD
SIPD
SEPD
SEPD
SEPD
SEPD
SEPD
SEPD
SEPD
SEPD
SIPD
SIPD
SIPD
SIPD
SIPD
SIPD
SIPD
SIPD
SIPD
SIPD
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
MSB
These peak detector registers allow the user to monitor the receive in signal (Sin) peak level at reference point S1 (see
Figure #1). The information is in 16-bit 2’s complement linear coded format presented in two 8 bit registers. The high byte
is in Register 2 and the low byte is in Register 1.
See above description
These peak detector registers allow the user to monitor the error signal peak level in the send path at reference point S2
(see Figure #1). The information is in 16-bit 2’s complement linear coded format presented in two 8 bit registers. The high
byte is in Register 2 and the low byte is in Register 1.
MSB
MSB
7
7
7
SIPD
SIPD
SEPD
15
7
7
6
6
6
SIPD
SIPD
SEPD
Send ERROR Peak Detect Register
14
Send (Sin) Peak Detect Register
6
Send (Sin) Peak Detect Register
6
5
5
5
SIPD
SIPD
SEPD
13
5
5
4
4
4
SIPD
SEPD
SIPD
12
4
4
3
3
3
SIPD
SIPD
SEPD
11
3
3
2
2
2
1 (SIPD1)
2 (SIPD2)
1 (SEPD1)
SIPD
SIPD
SEPD
10
2
2
1
1
1
SIPD
SIPD
SEPD
9
1
1
0
0
0
MT9315
SIPD
SIPD
SEPD
8
0
0
LSB
LSB
LSB
21

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