MT93L04A Zarlink Semiconductor, MT93L04A Datasheet - Page 31

• Manufacturer Part Number: MT93L04A
• Manufacturer: Zarlink Semiconductor

Preliminary Information
All pending interrupts from any of the echo cancellers and their associated input channel number are stored in
this FIFO memory. The IRQ always returns high after a read access to the Interrupt FIFO Register. The IRQ
pin will toggle low for each pending interrupt.
After the HOST CPU has received the channel number of the interrupt source, the corresponding per channel
Status Register can be read from internal memory to determine the cause of the interrupt (see Figure 7 for
address mapping of Status register). The TD bit indicates the presence of a Tone Disable.
The MIRQ bit 5 in the Main Control Register 0 masks interrupts from the MT93L00. To provide more flexibility,
the MTDBI (bit-4) and MTDAI (bit-3) bits in the Main Control Register<15:0> allow Tone Disable to be masked
or unmasked, from generating an interrupt on a per channel basis. Refer to the Registers Description section.
JTAG Support
The MT93L00 JTAG interface conforms to the Boundary-Scan standard IEEE1149.1. This standard specifies a
design-for-testability technique called Boundary-Scan test (BST). The operation of the Boundary Scan circuitry
is controlled by an external Test Access Port (TAP) controller. JTAG inputs are 3.3 Volts compliant only.
Test Access Port (TAP)
The TAP provides access to many test functions of the MT93L00. It consists of three input pins and one output
pin. The following pins are found on the TAP.
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Instruction Register
In accordance with the IEEE 1149.1 standard, the MT93L00 uses public instructions. The JTAG Interface
contains a 3-bit instruction register. Instructions are serially loaded into the instruction register from the TDI
when the TAP Controller is in its shifted-IR state. Subsequently, the instructions are decoded to achieve two
basic functions: to select the test data register that will operate while the instruction is current, and to define the
serial test data register path, which is used to shift data between TDI and TDO during data register scanning.
Test Clock Input (TCK)
Test Mode Select Input (TMS)
Test Data Input (TDI)
Test Data Output (TDO)
Test Reset (TRST)
The TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus re-
mains independent. The TCK permits shifting of test data into or out of the Boundary-Scan register cells con-
current with the operation of the device and without interfering with the on-chip logic.
The logic signals received at the TMS input are interpreted by the TAP Controller to control the test operations.
The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to V
not driven from an external source.
Serial input data applied to this port is fed either into the instruction register or into a test data register, depending
on the sequence previously applied to the TMS input. Both registers are described in a subsequent section. The
received input data is sampled at the rising edge of TCK pulses. This pin is internally pulled to V
not driven from an external source
Depending on the sequence previously applied to the TMS input, the contents of either the instruction register
or data register are serially shifted out towards the TDO. The data from the TDO is clocked on the falling edge
of the TCK pulses. When no data is shifted through the Boundary Scan cells, the TDO driver is set to a high
impedance state.
This pin is used to reset the JTAG scan structure. This pin is internally pulled to V
SS
.
MT93L04A
DD1
DD1
when it is
when it is
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