MTC20154-TQ-C2 ST Microelectronics, Inc., MTC20154-TQ-C2 Datasheet - Page 18

• Manufacturer Part Number: MTC20154-TQ-C2
• Description: Integrated Adsl CMOS Analog Front-end Circuit
• Manufacturer: ST Microelectronics, Inc.

MTC20154
Receive / Transmit Interface Timing
This interface is a triple (RX,TX, TXE) nibble-serial interface running at 8.8 MHz sampling (normal mode).
The data are represented in 16 bits format, and transferred in groups of 4 bits (nibbles). The LSBs are
transferred first. The MTC20154 generates a nibble clock (= master clock in normal mode, CLKNIB in
OSR = 2 mode) and word signals shared by the three interfaces.
Data is transmitted on the rising edge of the master clock (CLKM/CLKNIB) and sampled on the low going
edge of CLKM/CLKNIB. This holds for the data stream from MTC20154 and from the digital processor.
Data, CLWD setup and hold times are 5 ns with reference to the falling edge of CLKM/CLKNIB.
RXD is sampled with CLKM rising edge.
Figure 12. TX/TXE/RX Digital Interface Timing
Power Down
The MTC20154 is placed in power-down mode when the PD pin is high. The system specifications are
requiring different behavior of the MTC20154 under power down mode according to the fact that the
MTC20154 is used at the LT or the NT side. The chip status is depicted in the following table:
Table 23. Power Down
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CLKM pin is replicating the XTALO input clock
(no crystal used at LT side). System clock available
CLKWD is generated.
Digital blocks active
Analog TX path is in powerdown
External driver is forced to power UP
Power down LT side
CLKM
35.328 MHz
CLWD
TXDx/RXDx
CLKNIB
17.664 MHz
CLWD
4.416 MHz
TXDx/RXDx
8.832 MHz
N0
N0
N1
Crystal driver + VCODAC are active
CLKWD is generated.
Digital blocks active, except for RX–I/O’s – they are at low lovel
Analog RX & TX are in powerdown
External driver is forced to power DOWN
N2
N1
N3
OSR=2
Power down NT side
N2
N3