MT8804APR Zarlink Semiconductor, MT8804APR Datasheet - Page 6

• Manufacturer Part Number: MT8804APR
• Description: Description = 8 X 4 Analog Switch Array With Low On-resistance, For (VDD - VEE) = 5V to 15V ;; Package Type = Pdip ;; No. Of Pins = 24
• Manufacturer: Zarlink Semiconductor

MT8804A
NOTES:
3-8
Memory
Reset
MR
AE
ADDRESS
D0-D3
SWITCH
MR
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
↓
↓
↓
↓
↓
↓
↓
1 - High Logic Level
X - Don’t Care Condition
+ - Indicates Connection Between Junctor and Addressed Line
• - Indicates No Connection Between Junctor and Addressed Line
0 - Low Logic Level
ON
OFF
Address
Enable
AE
X
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
↓
↓
↓
↓
↓
↓
↓
CMOS
t
50%
AS
A2
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
↓
0
0
↓
0
0
↓
0
1
↓
1
1
↓
1
1
↓
1
1
↓
1
Address
50%
A1
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
↓
0
1
↓
1
1
↓
1
0
↓
0
0
↓
0
1
↓
1
1
↓
1
Figure 6 - Control Memory Timing Diagram
t
t
AEW
DS
50%
Table 1 - Address Decode Truth Table
A0
50%
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
↓
1
0
↓
0
1
↓
1
0
↓
0
1
↓
1
0
↓
0
1
↓
1
t
PLH
Addressed
NONE
/t
Line
ALL
PHL
L0
L0
L0
L0
L0
L0
L0
L0
L0
L0
L0
L0
L0
L0
L0
L0
L1
L1
L2
L2
L3
L3
L4
L4
L5
L5
L6
L6
L7
L7
t
↓
↓
↓
↓
↓
↓
↓
DH
50%
t
AH
50%
D3
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
↓
↓
↓
↓
↓
↓
↓
Input Data To Control
t
D2
PAE
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
50%
↓
↓
↓
↓
↓
↓
↓
Memory
D1
t
X
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
↓
↓
↓
↓
↓
↓
↓
PLH
/t
PHL
50%
D0
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
↓
1
0
↓
1
0
↓
1
0
↓
1
0
↓
1
0
↓
1
0
↓
1
t
MR
J3
+
+
+
+
+
+
+
+
↓
+
↓
+
↓
+
↓
+
↓
+
↓
+
↓
+
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Junctors Connected To
No Change of State
All Switches "OFF"
Addressed Line
J2
+
+
+
+
+
+
+
+
↓
+
↓
+
↓
+
↓
+
↓
+
↓
+
↓
+
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
t
MRR
50%
J1
+
+
+
+
+
+
+
+
↓
+
↓
+
↓
+
↓
+
↓
+
↓
+
↓
+
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
J0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
↓
↓
↓
↓
↓
↓
↓
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•