MT8910 Zarlink Semiconductor, MT8910 Datasheet - Page 6

• Manufacturer Part Number: MT8910
• Description: Digital Subscriber Line Interface Circuit
• Manufacturer: Zarlink Semiconductor

noted that the system interface has dedicated a full
64 kbit/s for the D-channel of which only the two first
bits (D0 and D1) are actually carrying information.
The other bits of the ST-BUS D-channel are reserved
for future use.
A third type of channel, the C-channel, is a non-
bearer channel which provides a means for the
system to control and monitor the functionality of the
DSLIC. This control/status channel is accessed by
the system through the ST-BUS.
provides access to three control registers and four
status registers which provide complete control or
status of all built-in features. Access to the control
register is provided by two bits in the Control
Register itself (CRS0 and CRS1). Selection of the
desired status register is performed using two bits in
Control Register 1 (SRS0 and SRS1).
channel also carries a control and status register for
the 4 kbit/s M-channel which can be used as an
additional
description of these registers is discussed in the ST-
BUS port interface section.
Line Code
The DSLIC transceiver uses the 2B1Q line code
which is a four level Pulse Amplitude Modulated
(PAM) code with no redundancy. The generation of
the 2B1Q signal is achieved by grouping two
consecutive bits into a bit field of which the first bit
represents the sign bit and the second represents
the magnitude.
codes as shown in Figure 3 (note that +3, +1, -1 and
-3 are only symbols and
voltage on the line).
The bit fields are grouped relative to the borders of
the defined channels where the first bit field consists
of bit 1 and bit 2 of the B1-channel, the second bit
field consists of bit 3 and bit 4 of the B1-channel
and so on.
+3
+1
-1
-3
QUATS -1
BITS
maintenance
time
0 1 1 0
+3
This yields four possible output
1 1
+1
channel.
they do not reflect the
0 0
-3
Figure 3 - Example of 2B1Q Quaternary Symbols
0 0
-3
The C-channel
1 1
+1
A
detailed
+3
1 0
The C-
0 0
-3
-1
0 1
Before converting the bit fields into output symbols,
all bits except the framing pattern are scrambled with
polynomials:
Framing
The frame structure in the DSLIC is 1.5 ms long and
consists of twelve 2B+D-channels delimited by the
framing pattern at the start of the frame and the
maintenance channel at the end. Framing for both
the LT and the NT is performed using a 9 symbol
synchronization word. This sync word (SW) has the
following structure:
Sync Word: +3, +3, -3, -3, -3, +3, -3, +3, +3
Eight DSLIC frames are grouped into a superframe
delimited by inverting the sync word (ISW):-3,-3, +3,
+3, +3, -3, +3, -3, -3. This second level of framing is
used to assign the M-channel bits as defined in the
ANSI T1.601-1988. The framing structure is shown
in Figure 4.
Transmission between the LT and NT is fully
synchronous.
boundaries between the NT receive frame and the
NT transmit frame have a fixed phase relationship.
The transmitted frame/superframe from the NT is
delayed by 60
respect to its received frame/superframe. Since the
NT extracts all its timing from the line, the DSLIC will
maintain the required phase relationship between
the frames and superframes and will insert the SW
and ISW during the proper time interval.
0 1
-1
(where
1 1
+1
0 1
-1
1
1
As such, the frame/superframe
2 quaternary symbols (quats) with
is modulo two summation)
-3
0 0
x
x
-5
-18
+3
1 0
x
x
-23
-23
1 0
+3
for LT
for NT
0 1
MT8910-1
-1
1 1
+1
9-7