MT8920 Zarlink Semiconductor, MT8920 Datasheet - Page 18
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MT8920
Manufacturer Part Number
MT8920
Description
32 Channels TDM (ST-BUS) to Parallel Bus Access Circuit
Manufacturer
Zarlink Semiconductor
Datasheet
1.MT8920.pdf
(27 pages)
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MT8920B
18
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25
testing.
AC Electrical Characteristics
(V
10
12
13
14
11
CC
1
2
3
4
5
6
7
8
9
=5.0V
A0 - A5
CS
OE
R/W
D0 - D7
OE Low to Valid Data
Address Access Time
CS Low to Valid Data
Output Disable
Address Setup Time
Data Setup Time
Data Hold Time
Address Hold Time
Write Pulse Width
OE, R/W High to C4i High
OE, R/W Low to C4i Low
C4i High to Busy Low
C4i Low to Busy High
OE, R/W High to Busy Low
±
5%,T
A
Characteristics
=-40 to 85
°
C, V
°
C)
DD
=5V, t
Figure 15 - Mode 2 Timing Diagram (No Contention)
CLK
t
AA
=244 ns, t
t
CSD
†
t
EVD
- Mode 2 Parallel Bus Timing - (see Figures 15 and 16)
t
t
t
t
Sym
t
t
t
t
t
t
EC4H
C4BH
t
EC4L
C4BL
t
CH
CSD
OHZ
t
EVD
t
ASF
DST
DHT
EBL
WP
AA
AH
=t
CL
=122 ns and are for design aid only: not guaranteed and not subject to production
Min
20
30
50
50
5
DATA OUT
Typ
-10
10
50
50
40
‡
t
OHZ
Max
120
60
60
50
t
ASF
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
WP
Load A, C
Load A, C
Load A, C
Load A, C
Load C
Load C
Load C
t
AH
t
DST
Test Conditions
DATA IN
L
L
L
L
=130pF, R
=130pF, R
=130pF, R
=130pF, R
Data Sheet
t
DHT
L
L
L
L
=740Ω
= 740Ω
=740Ω
=740Ω