MT8924 Zarlink Semiconductor, MT8924 Datasheet - Page 11

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MT8924

Manufacturer Part Number
MT8924
Description
PCM Conference Circuit (PCC)
Manufacturer
Zarlink Semiconductor
Datasheet

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MT8924
* All AC characteristics are valid 250 s after V
** With Extra Bit Insert operating mode this time becomes 3t
8-12
AC Electrical Characteristics - Clocked Timing*
10
11
12
13
14
15
resistor. With Extra Bit Insert operating mode these times are 80ns longer.
Cki
F0i
TD
TF
Cko
OS
1
2
3
4
5
6
7
8
9
Clock period
Clock low level width
Clock high level width
Clock rise time
Clock fall time
Sync. low setup time
Sync. low level hold time
Sync. high setup time
Sync. high width
OS propagation delay from rising
edge of Clock
Cko propagation delay to Clock
edges
TD setup time
TD hold time
TD setup time
TD hold time
Characteristics
t
WHCK
t
CK
t
WLCK
t
SLSY
DD
and the clock have been applied. C
t
t
STF
STD
t
t
HLSY
PDEC
t
t
t
t
t
t
Sym
t
t
WHCK
WHSY
WLCK
t
PDOS
t
t
t
SHSY
PDEC
t
t
SLSY
HLSY
Figure 5 - Clock Timing
t
RCK
FCK
STD
HTD
HTD
STF
CK
t
t
t
HTF
RCK
HTD
CK
t
.
t
t
PDOS
PDEC
SHSY
Min
230
100
100
t
t
50
40
80
80
40
80
40
FCK
CK
t
(T
WHSY
OP
Typ
=0 to 70 C; V
L
is the max. capacitive load and R
Max
100
25
25
80
DD
Preliminary Information
Units
=5V5%)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
**
C
C
L
L
Test Conditions
=50pF
=50pF
L
is the test pull up

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