MPC89L54A Megawin Technology, MPC89L54A Datasheet - Page 29

• Manufacturer Part Number: MPC89L54A
• Description: 8-bit micro-controller
• Manufacturer: Megawin Technology

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ISPEN: ISP function enabling bit
SWBS: Secondary Booting program selecting
SWRST: software reset trigger
SFR: SCMD (Sequential Command Data register for ISP):
SFR: ISPCR (ISP Control register):
Procedures demonstrating ISP function
Notice: Software reset actions could reset other SFR, but it never influences bits ISPEN and SWBS.
WAIT: Waiting time selection while the flash is busy.
SCMD is the command port for triggering ISP activity. If SCMD is filled with sequential 46h, B9h and if
ISPCR.7 = 1, ISP activity will be triggered.
When this register is read, the device ID of MPC89x54A will be returned (2 bytes). The MSB byte of DID is
F1h and LSB byte 04h. IFADRL[0] is used to select HIGH/LOW byte of DID.
MEGAWIN
Bit-7
Bit-7
ISPEN
0: = Disable ISP program to change flash
1: = Enable ISP program to change flash
0: = Boot from main-memory.
1: = Boot from ISP memory.
1: = Generate software system reset. It will be cleared by hardware automatically.
The ISPEN and SWBS only will be reset by power-up action, not software reset.
0: = No operation
SWBS
Bit-6
Bit-6
IFMT ← xxxxx011
ISPCR ← 100xx010
IFADRH ← (page address high byte)
IFADRL ← (page address low byte)
SCMD ← 46h
SCMD ← B9h
(CPU progressing will be hold here )
(CPU continues)
ISPCR[2:0]
0 0 0
0 0 1
0 1 0
0 1 1
SWRST
Bit-5
Bit-5
b
ISP-Command (Device ID)
b
Page Erase
MPC89x54A Data Sheet
Bit-4
Bit-4
43769
21885
10942
5471
-
Erase a specific flash page
CPU Wait time (Machine Cycle)
Bit-3
Bit-3
Program
-
240
120
60
30
/* set ISPEN=1 to enable flash change.
/* specify the address of the page to be erased */
/* choice page-erasing command */
set WAIT=010, 10942 MC; assumed 10M X’s*/
/* trig ISP activity */
Bit-2
Bit-2
Read
43
22
11
6
WAIT
Bit-1
Bit-1
Recommended
System clock
40M
20M
10M
5M
Bit-0
Bit-0
29