ADC0820CNED Philips Semiconductors, ADC0820CNED Datasheet - Page 2

• Manufacturer Part Number: ADC0820CNED
• Description: 8-Bit/ high-speed/ mP-compatible A/D converter with track/hold function
• Manufacturer: Philips Semiconductors

Philips Semiconductors Linear Products
BLOCK DIAGRAM
PIN DESCRIPTION
August 31, 1994
PIN NO
8-Bit, high-speed, P-compatible A/D converter with
track/hold function
1
2
3
4
5
6
7
8
9
V
DB0
DB1
DB2
DB3
WR/RDY
Mode
RD
INT
SYMBOL
IN
Analog input; range=GND V
3-state data output—Bit 0 (LSB)
3-state data output—Bit 1
3-state data output—Bit 2
3-state data output—Bit 3
WR-RD Mode
WR: With CS Low, the conversion is started on the falling edge of WR. Approximately 800ns (the preset internal time
out, t
does not occur prior to this time out (see Figures 3a and 3b).
RD Mode
RDY: This is an open-drain output (no internal pull-up device). RDY will go Low after the falling edge of CS; RDY will
go 3-State when the result of the conversion is strobed into the output latch. It is used to simplify the interface to a
microprocessor system (see Figure 1).
Mode: Mode selection input—it is internally tied to GND through a 30 A current source.
RD Mode: When mode is Low.
WR-RD Mode: When mode is High.
WR-RD Mode
With CS Low, the 3-State data outputs (DB0-DB7) will be activated when RD goes Low. RD can also be used to
increase the speed of the converter by reading data prior to the preset internal time out (T
the data result transferred to output latch is latched after the falling edge of the RD (see Figures 3a and 3b).
RD Mode
With CS Low, the conversion will start with RD going Low; also, RD will enable the 3-State data outputs at the
completion of the conversion. RDY going 3-State and INT going Low indicate the completion of the conversion (see
Figure 1).
WR-RD Mode
INT going Low indicates that the conversion is completed and the data result is in the output latch. INT will go
Low ~ 800ns (the preset internal time out, t
the falling edge of RD, if RD goes Low prior to the 800ns time out (see Figure 3b). INT is reset by the rising edge of
RD or CS (see Figures 3a and 3b).
V
I
IN
) after the WR rising edge, the result of the conversion will be strobed into the output latch, provided that RD
+
V
V
V
V
V
V
16
–
REF
REF
REF
REF
REF
REF
IN
(+)
(+)
(–)
(+)
(–)
(–)
V
DD
MODE
(4MSBs)
(4LSBs)
4–BIT
FLASG
FLASG
DAC
4–BIT
4–BIT
TIMING AND CONTROL CIRCUITRY
ADC
ADC
569
I
) after the rising edge of WR (see Figure 3a); or INT will go Low after
OFL
WR/RDY
DESCRIPTION
CS
THREE–STATE
BUFFERS
OUTPUT
LATCH
AND
RD
OFL
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
INT
I
~ 800ns). If this is done,
Product specification
ADC0820