ADC1175-50CIMT National Semiconductor, ADC1175-50CIMT Datasheet - Page 3

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ADC1175-50CIMT

Manufacturer Part Number
ADC1175-50CIMT
Description
8-Bit/ 50 MSPS/ 125 mW A/D Converter
Manufacturer
National Semiconductor
Datasheet

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13, 14
3 thru
Pin Descriptions and Equivalent Circuits
2, 24
No.
Pin
11,
22
12
10
1
Symbol
D0–D7
DV
DV
V
CLK
PD
RBS
DD
SS
Equivalent Circuit
3
(Continued)
Reference Bottom Bias with internal pull down
resistor. Short to V
ladder. Bypass well if not grounded. See Section
2.0 for more information.
CMOS/TTL compatible Digital input that, when high,
puts the ADC1175-50 into a power-down mode
where total power consumption is typically less than
5 mW. With this pin low, the device is in the normal
operating mode.
CMOS/TTL compatible digital clock input. V
sampled on the falling edge of CLK input.
Conversion data digital Output pins. D0 is the LSB,
D7 is the MSB. Valid data is output just after the
rising edge of the CLK input. These pins are in a
high impedance mode when the PD pin is low.
Positive digital supply pin. Connect to a clean, quiet
voltage source of +5V. AV
a common source and be separately bypassed with
a 10 µF capacitor and a 0.1 µF ceramic chip
capacitor. See Section 4.0 for more information.
The ground return for the digital supply. AV
DV
ADC1175-50.
SS
should be connected together close to the
RB
Description
to self-bias the reference
DD
and DV
DD
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should have
SS
IN
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