ADC12062 National Semiconductor, ADC12062 Datasheet
ADC12062
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ADC12062 Summary of contents
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... A D without the cost and power dissipation associated with true flash ap- proaches The analog input voltage to the ADC12062 is tracked and held by an internal sampling circuit allowing high frequency input signals to be accurately digitized without the need for ...
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... CC Storage Temperature Range 25 mA Maximum Junction Temperature ( 875 mW Operating Ratings 2000V Temperature Range ADC12062BIV ADC12062CIV ADC12062BIVF ADC12062CIVF Supply Voltage Range (DV The following specifications apply for MHz unless otherwise specified Boldface limits apply for Typ Conditions (Note 7) T ...
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Dynamic Characteristics V 4 096V REF (SENSE) REF (SENSE otherwise specified Boldface limits apply for T Symbol Parameter SINAD Signal-to-Noise Plus Distortion Ratio SNR Signal-to-Noise Ratio (Note 11) THD Total Harmonic Distortion (Note 12) ENOB ...
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AC Electrical Characteristics V 4 096V REF (SENSE) REF (SENSE for T T from all other limits MIN MAX Symbol Parameter f Maximum Sampling Rate ...
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... Note 9 Integral Linearity Error is the maximum deviation from a straight line between the measured offset and full scale endpoints Note 10 Dynamic testing of the ADC12062 is done using the ADC IN input The input multiplexer adds harmonic distortion at high frequencies See the graph in the Typical Performance Characteristics section for a typical graph of THD performance vs input frequency with and without the input multiplexer ...
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Typical Performance Characteristics Offset and Fullscale Error Change vs Reference Voltage Digital Supply Current vs Temperature Conversion Time (t ) CONV vs Temperature SINAD vs Input Frequency (ADC IN) Linearity Error Change Mux ON Resistance vs vs Reference Voltage Input ...
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Typical Performance Characteristics SINAD vs Input Frequency (Through Mux) SNR and THD vs Source Impedance Timing Diagrams FIGURE 1 Interrupt Interface Timing (MODE (Continued) SNR vs Input Frequency THD vs Input Frequency (Through Mux) (Through Mux) SNR and THD vs ...
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Timing Diagrams (Continued) FIGURE 2 High Speed Interface Timing (MODE FIGURE 3 CS Setup and Hold Timing for and OE Connection Diagrams Top View 11490 – ...
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... AGND above This pin selects the analog input that will be connected to the ADC12062 during the conversion The input is selected based on the state of S0 when EOC makes its high- to-low transition Low selects V selects V IN2 ...
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... Functional Description The ADC12062 performs a 12-bit analog-to-digital conver- sion using a 3 step flash technique The first flash deter- mines the six most significant bits the second flash gener- ates four more bits and the final flash resolves the two least ...
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... Applications Information REF 1 0 MODES OF OPERATION The ADC12062 has two interface modes An interrupt read mode and a high speed mode Figures 1 and 2 show the timing diagrams for these interfaces In order to clearly show the relationship between and OE the control logic decoding section of the ...
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... Applications Information (Continued THE ANALOG INPUT The analog input of the ADC12062 can be modeled as two small resistances in series with the capacitance of the input hold capacitor ( shown in Figure 7 The S H switch IN is closed during the Sample period and open during Hold ...
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... Applications Information (Continued) FIGURE 8 Buffering the Input with an LM6361 High Speed Op Amp Another benefit of using a high speed buffer is improved THD performance when using the multiplexer of the ADC12062 The MUX on-resistance is somewhat non-linear over input voltage causing the RC time constant formed and R ...
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... LSBs The ADC12062 provides a means to eliminate this error by bringing out two additional pins that sense the exact voltage at the top and bottom of the ladder With the addition of two ...
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... The V output should be bypassed to analog REF 16 ground with ceramic capacitor The LM4040 shunt voltage reference is available with a 4 096V output voltage With initial accuracies as low makes an excellent reference for the ADC12062 g Force Pins Only REF ...
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... S H input As long as the duty cycle is near 50% the waveform will be low for about 500 ns which is within the 550 ns limit When operating the ADC12062 at a sample rate of 910 kHz or below the pulse width of the S H signal must be smaller than half the sample period ...
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... The S H pulse stream for the converter appears on the Q output of the HC4538 This is the S H clock generator used on the ADC12062EVAL evaluation board For lower power a CMOS inverter-based crystal oscillator can be used in place of the DIP crystal oscillator See Application Note ...
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Applications Information (Continued) AC Coupling Bipolar Inputs 11490 – 26 ...
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... Physical Dimensions inches (millimeters) Order Number ADC12062BIV ADC12062CIV Plastic Leaded Chip Carrier (V) NS Package Number V44A 19 ...
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... Physical Dimensions inches (millimeters) (Continued) Order Number ADC12062BIVF ADC12062CIVF LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or ...