PIC14000-04 Microchip Technology, PIC14000-04 Datasheet - Page 39
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC14000-04
Manufacturer Part Number
PIC14000-04
Description
28-Pin Programmable Mixed Signal Controller
Manufacturer
Microchip Technology
Datasheet
1.PIC14000-04.pdf
(152 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC14000-04/SO
Manufacturer:
Microchip Technology
Quantity:
135
Company:
Part Number:
PIC14000-04/SO
Manufacturer:
Maxim
Quantity:
103
Company:
Part Number:
PIC14000-04/SP
Manufacturer:
Microchip
Quantity:
482
Part Number:
PIC14000-04/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Company:
Part Number:
PIC14000-04/SS
Manufacturer:
Microchip Technology
Quantity:
135
Part Number:
PIC14000-04/SS
Manufacturer:
MICROCHI
Quantity:
20 000
6.2
When the external clock input (pin RC3/T0CKI) is used
for Timer0, it must meet certain requirements. The
external clock requirement is due to internal phase
clock (T
the actual incrementing of TMR0 after synchronization.
6.2.1
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks
(Figure 6-5). Therefore, it is necessary for T0CKI to be
high for at least 2Tosc (and a small RC delay of 20 ns)
and low for at least 2Tosc (and a small RC delay of
20 ns).
When a prescaler is used, the external clock input is
divided by the asynchronous ripple counter-type
prescaler so that the prescaler output is symmetrical.
For the external clock to meet the sampling
requirement, the ripple counter must be taken into
account. Therefore, it is necessary for T0CKI to have a
period of at least 4Tosc (and a small RC delay of 40 ns)
divided by the prescaler value. The only requirement
on T0CKI high and low time is that they do not violate
the minimum pulse width requirement of 10 ns.
FIGURE 6-5:
1996 Microchip Technology Inc.
T0CKI
OSC
Using Timer0 with External Clock
EXTERNAL CLOCK SYNCHRONIZATION
OUTPUT AFTER SAMPLING
PRESCALER OUT (NOTE 2)
Notes:
1.
2.
3.
EXT CLOCK/PRESCALER
) synchronization. Also, there is a delay in
with
Delay from clock input change to TMR0 increment is 3 T
Therefore, the error in measuring the interval between two edges on TMR0 input =
External clock if no prescaler selected, Prescaler output otherwise.
The arrows indicate the points in time where sampling occurs.
INCREMENT TMR0 (Q4)
EXT CLOCK INPUT OR
TIMER0 TIMING WITH EXTERNAL CLOCK
the
internal
TMR0
phase
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
clocks
Preliminary
is
T0
6.2.2
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0
module is actually incremented. Figure 6-5 shows the
delay from the external clock edge to the timer
incrementing.
6.3
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a post-scaler for the Watchdog
Timer (Figure 6-1). For simplicity, this counter is being
referred to as “prescaler” throughout this data sheet.
Note that there is only one prescaler available which is
mutually exclusive between the Timer0 module and the
Watchdog Timer. Thus, a prescaler assignment for the
Timer0 module means that there is no prescaler for the
Watchdog Timer, and vice-versa.
Bit PSA and PS2:PS0 (OPTION<3:0>) determine the
prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the Timer0 module (e.g., CLRF 1, MOVWF 1,
BSF 1,x ) will clear the prescaler. When assigned to
WDT, a CLRWDT instruction will clear the prescaler
along with the Watchdog Timer. The prescaler is not
readable or writable.
OSC
to 7 T
TIMER0 INCREMENT DELAY
Prescaler
OSC
. (Duration of Q = T
T0 + 1
4 tosc max.
PIC14000
(note 3)
OSC
).
T0 + 2
Small pulse
misses sampling
DS40122B-page 39