BSP3505D Micronas Intermetall GmbH, BSP3505D Datasheet - Page 7

• Manufacturer Part Number: BSP3505D
• Manufacturer: Micronas Intermetall GmbH

Micronas
PRELIMINARY DATA SHEET
3. I
As a slave receiver, the BSP 3505D can be controlled via
I
achieved by subaddressing. The DSP processor part
has its own subaddressing register bank.
In order to allow for more BSP or MSP ICs to be con-
nected to the control bus, an ADR_SEL pin has been im-
plemented. With ADR_SEL pulled to high, low, or left
open, the BSP 3505D responds to changed device ad-
dresses. Thus, three identical devices can be selected.
By means of the RESET bit in the CONTROL register,
all devices with the same device address are reset.
The IC is selected by asserting a special device address
in the address part of an I
dress pair is defined as a write address (80, 84, or 88
and a read address (81, 85, or 89
sending the device write address first, followed by the
subaddress byte, two address bytes, and two data by-
tes. Reading is done by sending the device write ad-
dress, followed by the subaddress byte and two address
bytes. Without sending a stop condition, reading of the
addressed data is completed by sending the device read
address (81, 85, or 89
Refer to Fig. 3–1: I
posal for BSP 3505D I
Table 3–1: I
Table 3–2: I
2
C bus. Access to internal memory locations is
ADR_SEL
Mode
BSP device address
Name
CONTROL
TEST
WR_DSP
RD_DSP
2
C Bus Interface: Device and Subaddresses
2
2
C Bus Device Addresses
C Bus Subaddresses
2
C Bus Protocol and section 3.2. Pro-
hex
2
C Telegrams.
) and reading two bytes of data.
2
Binary Value
0000 0000
0000 0001
0001 0010
0001 0011
C transmission. A device ad-
Write
80
hex
hex
). Writing is done by
Low
Read
81
hex
Hex Value
00
01
12
13
hex
)
Write
84
Due to the internal architecture of the BSP 3505D the IC
cannot react immediately to an I
response time is about 0.3 ms for the DSP processor
part. If the receiver (BSP) can’t receive another com-
plete byte of data until it has performed some other func-
tion; for example, servicing an internal interrupt, it can
hold the clock line I
into a wait state. The positions within a transmission
where this may happen are indicated by ’Wait’ in section
3.1. The maximum Wait-period of the BSP during normal
operation mode is less than 1 ms.
I
In case of any internal error, the BSPs wait-period is ex-
tended to 1.8 ms. Afterwards, the BSP does not ac-
knowledge (NAK) the device address. The data line will
be left HIGH by the BSP and the clock line will be re-
leased. The master can then generate a STOP condition
to abort the transfer.
By means of NAK, the master is able to recognize the er-
ror state and to reset the IC via I
ting the reset protocol (s. 5.2.4.) to ‘CONTROL’, the
master must ignore the not acknowledge bits (NAK) of
the BSP.
A general timing diagram of the I
Fig. 3–2.
hex
2
C-Bus conditions caused by BSP hardware problems:
Mode
Write
Write
Write
Write
High
Read
85
hex
2
C_CL LOW to force the transmitter
Function
software reset
only for internal use
write address DSP
read address DSP
Write
88
hex
2
2
C-Bus. While transmit-
C request. The typical
BSP 3505D
Left Open
2
C Bus is shown in
Read
89
hex
7