PIC16C65A Microchip Technology, PIC16C65A Datasheet - Page 65

• Manufacturer Part Number: PIC16C65A
• Description: 8-Bit CMOS Microcontrollers
• Manufacturer: Microchip Technology

7.0
The Timer0 module has the following features:
• 8-bit timer/counter register, TMR0
• 8-bit software programmable prescaler
• Internal or external clock select
Figure 7-1 is a simplified block diagram of the Timer0
module.
Timer mode is selected by clearing bit T0CS
(OPTION<5>). In timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
TMR0 register is written, the increment is inhibited for
the following two instruction cycles (Figure 7-2 and
Figure 7-3). The user can work around this by writing
an adjusted value to the TMR0 register.
Counter mode is selected by setting bit T0CS. In this
mode, Timer0 will increment either on every rising or
falling edge of pin RA4/T0CKI. The incrementing edge
is determined by the source edge select bit T0SE
FIGURE 7-1:
FIGURE 7-2:
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
1997 Microchip Technology Inc.
- Read and write capability
- Interrupt on overflow from FFh to 00h
- Edge select for external clock
Instruction
TMR0
PC
(Program
Counter)
Fetch
Instruction
Executed
RA4/T0CKI
pin
Note 1:
TIMER0 MODULE
2: The prescaler is shared with Watchdog Timer (refer to Figure 7-6 for detailed diagram).
T0SE
Bits, T0CS, T0SE, PSA, and PS2, PS1, PS0 are (OPTION<5:0).
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
T0
F
TIMER0 BLOCK DIAGRAM
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALER
OSC
PC-1
/4
MOVWF TMR0
T0+1
T0CS
PC
0
1
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
T0+2
Write TMR0
executed
PS2, PS1, PS0
Programmable
PC+1
Prescaler
3
NT0
Read TMR0
reads NT0
PC+2
PSA
1
0
(OPTION<4>). Clearing bit T0SE selects the rising
edge. Restrictions on the external clock input are dis-
cussed in detail in Section 7.2.
The prescaler is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. The pres-
caler assignment is controlled in software by control bit
PSA (OPTION<3>). Clearing bit PSA will assign the
prescaler to the Timer0 module. The prescaler is not
readable or writable. When the prescaler is assigned to
the Timer0 module, prescale values of 1:2, 1:4, ...,
1:256 are selectable. Section 7.3 details the operation
of the prescaler.
7.1
The TMR0 interrupt is generated when the register
(TMR0) overflows from FFh to 00h. This overflow sets
interrupt flag bit T0IF (INTCON<2>). The interrupt can
be masked by clearing enable bit T0IE (INTCON<5>).
Flag bit T0IF must be cleared in software by the TImer0
interrupt service routine before re-enabling this inter-
rupt. The TMR0 interrupt cannot wake the processor
from SLEEP since the timer is shut off during SLEEP.
Figure 7-4 displays the Timer0 interrupt timing.
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
PSout
Read TMR0
reads NT0
NT0
PC+3
(2 cycle delay)
Sync with
TMR0 Interrupt
Internal
clocks
MOVF TMR0,W
Read TMR0
reads NT0
NT0
PC+4
PSout
MOVF TMR0,W
Read TMR0
reads NT0 + 1
TMR0 reg
NT0+1
PIC16C6X
Data bus
PC+5
8
DS30234D-page 65
Read TMR0
reads NT0 + 2
Set bit T0IF
on overflow
NT0+2
PC+6