BD9540EFV ROHM Electronics, BD9540EFV Datasheet - Page 16

• Manufacturer Part Number: BD9540EFV
• Description: 2ch Switching Regulators for Desktop PC
• Manufacturer: ROHM Electronics

●Power Dissipation
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BD9540EFV
www.rohm.com
Parasitic element
(11) Regarding input pins of the IC
(12)Ground Wiring Pattern
Pin A
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. PN junctions are formed at the intersection of these P layers with the N layers of other elements, creating
parasitic diodes and/or transistors. For example (refer to the figure below):
Parasitic diodes occur inevitably in the structure of the IC, and the operation of these parasitic diodes can result in
mutual interference among circuits, operational faults, or physical damage. Accordingly, conditions that cause these
diodes to operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate)
should be avoided.
When using both small-signal and large-current GND traces, the two ground traces should be routed separately but
connected to a single ground potential within the application in order to avoid variations in the small-signal ground
caused by large currents. Also ensure that the GND traces of external components do not cause variations on GND
voltage.
N
P
+
 When GND > Pin A and GND > Pin B, the PN junction operates as a parasitic diode
 When GND > Pin B, the PN junction operates as a parasitic transistor
1.0
4.0
3.0
5.0
2.0
N
0
0
④ 4.70W
③ 3.30W
② 1.85W
① 1.45W
GND
P
25
P substrate
Ambient temperature :Ta [℃]
P
+
N
Resistor
50
Pin A
75
100
Parasitic
element
125
Example of IC structure
Parasitic element
Pin B
N
150
16/17
①Mounted on board 70mm×70mm×1.6mm glass-epoxy PCB, 1 layer
②Mounted on board 70mm×70mm×1.6mm glass-epoxy PCB, 2 layers,
③Mounted on board 70mm×70mm×1.6mm glass-epoxy PCB, 2 layers,
④Mounted on board 70mm×70mm×1.6mm glass-epoxy PCB, 4 layers,
P
+
No copper foil area. θj-a=86.2℃/W
Copper foil area : 15mm×15mm, θj-a=67.6℃/W
Copper foil area :: 70mm×70mm, θj-a=37.9℃/W
Copper foil area :: 70mm×70mm, θj-a=26.6℃/W
C
B
N
E
GND
P
P substrate
Transistor (NPN)
P
+
N
GND
Other adjacent elements
Pin B
B
C
E
Technical Note
2009.04 - Rev.B
GND
Parasitic
element