EMC2103 Standard Microsystems Corporation, EMC2103 Datasheet - Page 47

• Manufacturer Part Number: EMC2103
• Description: Rpm-based Fan Controller with HW Thermal Shutdown
• Manufacturer: Standard Microsystems Corporation

ADDR
1Dh
1Ah
1Bh
19h
RPM-Based Fan Controller with HW Thermal Shutdown
Datasheet
SMSC EMC2103
6.9
6.10
ADDR
20h
once
once
once
once
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The Critical Temperature Limit Registers store the Critical Temperature Limit. At power up, none of the
respective channels are linked to the SYS_SHDN pin or the Hardware set Thermal/Critical Shutdown
circuitry.
Whenever one of the registers is updated, two things occur. First, the register is locked so that it cannot
be updated again without a power on reset. Second, the respective temperature channel is linked to
the SYS_SHDN pin and the Hardware set Thermal/Critical Shutdown Circuitry. At this point, if the
measured temperature channel exceeds the Critical limit, the SYS_SHDN pin will be asserted, the
appropriate bit set in the Tcrit Status Register, and the TCRIT bit in the Interrupt Status Register will
be set.
The Configuration Register controls the basic functionality of the EMC2103. The bits are described
below.
Bit 7 - MASK - Blocks the ALERT pin from being asserted.
Bit 3 - SYS3 (EMC2103-2 only) - Enables the high temperature limit for the External Diode 3 channel
to trigger the Critical / Thermal Shutdown circuitry (see
Bit 2 - SYS2 (EMC2103-2 only) - Enables the high temperature limit for the External Diode 2 channel
to trigger the Critical / Thermal Shutdown circuitry (see
Critical Temperature Limit Registers
Configuration Register
‘0’ (default) - The ALERT pin is unmasked. If any bit in either status register is set, the ALERT pin
will be asserted (unless individually masked via the Mask Register)
‘1’ - The ALERT pin is masked and will not be asserted.
‘0’ (default) - the External Diode 3 channel high limit will not be linked to the SYS_SHDN pin. If the
temperature meets or exceeds the limit, the ALERT pin will be asserted normally.
‘1’ - the External Diode 3 channel high limit will be linked to the SYS_SHDN pin. If the temperature
meets or exceeds the limit then the SYS_SHDN pin will be asserted. The SYS_SHDN# pin will be
released when the temperature drops below the high limit. The ALERT pin will be asserted
normally.
External Diode
External Diode
External Diode
Configuration
Internal Diode
REGISTER
1 Tcrit Limit
2 Tcrit Limit
3 Tcrit Limit
REGISTER
Tcrit Limit
MASK
B7
Sign
Sign
Sign
Sign
B7
Table 6.14 Configuration Register
Table 6.13 Limit Registers
-
B6
B6
64
64
64
64
DATASHEET
-
B5
47
B5
32
32
32
32
-
B4
B4
16
16
16
16
SYS3
B3
Section
Section
B3
8
8
8
8
SYS2
B2
5.1).
5.1).
B2
4
4
4
4
SYS1
B1
B1
2
2
2
2
Revision 0.85 (01-29-08)
APD
B0
B0
1
1
1
1
DEFAULT
00h
DEFAULT
(+100°C)
(+100°C)
(+100°C)
(+100°C)
64h
64h
64h
64h