74ABT162244CSSC Fairchild Semiconductor, 74ABT162244CSSC Datasheet
74ABT162244CSSC
Manufacturer Part Number
74ABT162244CSSC
Description
IC BUFF DVR TRI-ST 16BIT 48SSOP
Manufacturer
Fairchild Semiconductor
Series
74ABTr
Datasheet
1.74ABT162244CSSC.pdf
(5 pages)
Specifications of 74ABT162244CSSC
Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
4
Number Of Bits Per Element
4
Current - Output High, Low
32mA, 64mA
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74ABT162244CSSC
Manufacturer:
ON/安森美
Quantity:
20 000
© 1999 Fairchild Semiconductor Corporation
FST16209MEA
FST16209MTD
FST16209
18-Bit Bus Exchange Switch
General Description
The Fairchild Switch FST16209 provides 18-bits of high-
speed CMOS TTL-compatible bus switching or exchang-
ing. The low on resistance of the switch allows inputs to be
connected to outputs without adding propagation delay or
generating additional ground bounce noise.
The device operates as a 18-bit bus switch or a 9-bit bus
exchanger, which allows data exchange between the four
signal ports via the data-select terminals.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Diagram
Truth Table
Order Number
S2
H
H
H
H
L
L
L
L
S1
H
H
H
H
L
L
L
L
S0
H
H
H
H
L
L
L
L
Package Number
A
B
B
B
B
Z
Z
Z
Z
MS48A
MTD48
1
1
2
1
2
A
B
B
B
B
Z
Z
Z
Z
2
1
2
2
1
A
A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
1
1
Disconnect
Disconnect
Function
A
A
A
A
B
B
1
1
2
2
1
2
, A
, A
DS500056
B
B
B
B
2
2
1
2
1
2
B
B
2
1
Features
Connection Diagram
Pin Descriptions
4 switch connection between two ports.
Minimal propagation delay through the switch.
Low l
Zero bounce in flow-through mode.
Control inputs compatible with TTL level.
S2, S1, S0
Pin Name
CC
Package Description
A
B
.
1
1
, A
, B
2
2
September 1997
Revised December 1999
Data-select inputs
Description
Bus A
Bus B
www.fairchildsemi.com
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74ABT162244CSSC Summary of contents
Page 1
... © 1999 Fairchild Semiconductor Corporation Features 4 switch connection between two ports. Minimal propagation delay through the switch. Low Zero bounce in flow-through mode. Control inputs compatible with TTL level. Package Description Connection Diagram Function Disconnect Pin Descriptions Pin Name 2 2 Disconnect S2, S1, S0 ...
Page 2
Absolute Maximum Ratings Supply Voltage ( Switch Voltage ( Input Voltage (V )(Note Input Diode Current ( Output (I ) Sink Current OUT DC V ...
Page 3
AC Electrical Characteristics Symbol Parameter Prop Delay Bus to Bus (Note 6) PHL PLH Prop Delay S to Bus PHL PLH Output Enable Time PZH PZL ...
Page 4
Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide www.fairchildsemi.com Package Number MS48A 4 ...
Page 5
Physical Dimensions Physical Dimensions inches (millimeters) unless otherwise noted (Continued) inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Technology Description The Fairchild Switch family derives from and embodies Fairchild’s proven switch ...