KSC-1000 Kodak, KSC-1000 Datasheet - Page 32

• Manufacturer Part Number: KSC-1000
• Description: Timing Generator Full Program-ability Through a Simple 3-wire Serial Interface Allows Maximum Flexibility in Sensor Operation.
• Manufacturer: Kodak

IMAGE SENSOR SOLUTIONS
32
Data Length
Width Register
This register controls the width of the signals
listed below.
1/64
length, providing a maximum width of ½ the pixel
period. The Offset Register Setting positions the
leading edge of these signals. The trailing edge
of these signals is positioned by setting of this
Frame Table Access Register
The Frame Table Access Register is used to
program the Frame Tables. The Frame Tables
can only be programmed in low power mode or
when the Memory Table Mode bit of the General
Purpose Control Register is set to Programming
Mode. There are 8 unique Frame Tables. Each
Frame Table can contain up to 16 entries. Frame
tables can be concatenated together to form very
complex sensor clocking patterns.
K S C - 1 0 0 0 R e v 1 . 0
Register 7
5 bits
5 bits
5 bits
5 bits
5 bits
5 bits
5 bits
5 bits
5 bits
5 bits
5 bits
5 bits
5 bits
th
the pixel period. Each entry is 5 bits in
w w w . k o d a k . c o m / g o / i m a g e r s
H1_1 WIDTH (0 = ¼ duty cycle, 16 = ½ duty cycle, 31 = 47/64 duty cycle)
H1_2 WIDTH (0 = ¼ duty cycle, 16 = ½ duty cycle, 31 = 47/64 duty cycle)
H2_1 WIDTH (0 = ¼ duty cycle, 16 = ½ duty cycle, 31 = 47/64 duty cycle)
H2_2 WIDTH (0 = ¼ duty cycle, 16 = ½ duty cycle, 31 = 47/64 duty cycle)
HLG_1 WIDTH (0 = ¼ duty cycle, 16 = ½ duty cycle, 31 = 47/64 duty cycle)
HLG_2 WIDTH (0 = ¼ duty cycle, 16 = ½ duty cycle, 31 = 47/64 duty cycle)
RG_WIDTH (0 = ½ duty cycle, 1 = 1/64 duty cycle, 31 = 31/64 duty cycle)
SHP_1_WIDTH (0 = ½ duty cycle, 1 = 1/64 duty cycle, 31 = 31/64 duty cycle)
SHP_2_WIDTH (0 = ½ duty cycle, 1 = 1/64 duty cycle, 31 = 31/64 duty cycle)
SHD_1_WIDTH (0 = ½ duty cycle, 1 = 1/64 duty cycle, 31 = 31/64 duty cycle)
SHD_2_WIDTH (0 = ½ duty cycle, 1 = 1/64 duty cycle, 31 = 31/64 duty cycle)
ADCLK_WIDTH (0 = ¼ duty cycle, 16 = ½ duty cycle, 31 = 47/64 duty cycle)
DATA_CLK_WIDTH (0 = ¼ duty cycle, 16 = ½ duty cycle, 31 = 47/64 duty cycle)
The width is defined in units of
Table 19 Width Register Map
The Count
5 8 5 - 7 2 2 - 4 3 8 5
Width Register
Register Field
register relative to the setting of the Offset
Register.
DATACLK outputs are adjustable from 1/4 duty
cycle to 47/64 duty cycle. The SHP, SHD, and
RG outputs are adjustable from 1/64 duty cycle to
½ duty cycle.
and Flag fields together with VD signal control the
sequencing from Frame Table to Frame Table as
well as looping within a frame table
The frame table address needs to be written only
once during programming.
group of 34 bits programs a row in the frame
table. Programming automatically sequences to
the next Frame Table number.
E m a i l : i m a g e r s @ k o d a k . c o m
The H1, H2, HLG, ADCLK, and
Each subsequent
(Decimal)
Default
16
16
16
16
16
16
14
14
14
14
16
16
7