R1610C RDC Semiconductor, R1610C Datasheet - Page 68

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R1610C

Manufacturer Part Number
R1610C
Description
High Performance 16 Bits MCU Integrated One 10/100M Mac Controller - 3.3V Operating Voltage/2.5V Core Voltage
Manufacturer
RDC Semiconductor
Datasheet
R
R
15-0 TC[15:0]
12-6
68
Register Offset:
Register Name:
Reset Value
Register Offset:
Register Name:
Reset Value
EN
4-1
15
Bit
15
Bit
15
14
13
5
0
D
D
INH_n
14
14
INH_n
CONT
Name
Name
Rsvd
Rsvd
C
C
INT
MC
EN
INT
13
13
®
®
:
:
Attribute
Attribute
R
R
I
I
S
S
C
C
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
5Ch
Timer 1 Maxcount Compare B Register
──
66h
Timer 2 Mode/Control Register
0000h
D
D
12
12
0
S
S
P
P
C
C
o
o
m
m
m
m
u
u
11
11
n
n
Timer 1 Compare B Value.
0
Enable Bit.
Set 1: Timer 2 is enabled.
Set 0: Timer 2 is inhibited from counting.
The INH_n bit must be set to 1 during writing the EN bit, and the INH_n and EN bit
must be in the same write.
Inhibit Bit.
This bit allows selective updating the EN bit. The INH_n bit must be set to 1 during
writing the EN bit, and both the INH_n and EN bit must be in the same write. This bit
is not stored and is always read as 0.
Interrupt Bit.
Set 1: An interrupt request is generated when the count register equals a maximum
Set 0: Timer 2 will not issue interrupt request.
Reserved
Maximum Count Bit.
When the timer reaches its maximum count, the MC bit will be set to 1 by H/W. This
bit is set regardless of the EN bit (66h.15).
Reserved
Continuous Mode Bit.
Set 1: The timer is continuously running when it reaches the maximum count.
Set 0: The EN bit (66h [15]) is cleared and the timer is held after each timer count
i
i
c
c
a
a
t
t
i
i
o
o
n
n
10
10
0
count.
reaches the maximum count.
9
9
0
8
8
0
TC [15:0]
7
7
0
6
6
0
Description
Description
MC
5
5
4
4
0
Fast Ethernet RISC Processor
3
3
0
2
2
0
1
1
0
R1610C
CONT
October 27, 2003
0
0
Final Version 1.5
Data Sheet

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