74ABT16952CSSCX Fairchild Semiconductor, 74ABT16952CSSCX Datasheet
74ABT16952CSSCX
Specifications of 74ABT16952CSSCX
Related parts for 74ABT16952CSSCX
74ABT16952CSSCX Summary of contents
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... L LOW Voltage Level LOW-to-HIGH Transition X Immaterial NC No Change © 2001 Fairchild Semiconductor Corporation Features Separate clock, clock enable and 3-STATE output enable provided for each register A and B output sink capability source capability Guaranteed latchup protection High impedance glitch free bus loading during entire ...
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Block Diagram n for either byte 1 or byte 2 www.fairchildsemi.com 2 ...
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Absolute Maximum Ratings Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias V Pin Potential to Ground Pin CC Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disable or Power-Off State in ...
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AC Electrical Characteristics (SSOP Package) Symbol Parameter f Maximum Clock Frequency MAX t Propagation Delay PLH t CPAB or CPBA PHL Output Enable Time PZH t OEAB or OEBA to A ...
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AC Loading *Includes jig and probe capacitance FIGURE 1. Standard AC Test Load Amplitude 3.0V FIGURE 3. Input Signal Requirements AC Waveforms FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 5. Propagation Delay, Pulse Width Waveforms FIGURE ...
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Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide www.fairchildsemi.com Package Number MS56A 6 ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...