SDA4336 Infineon Technologies Corporation, SDA4336 Datasheet - Page 30

• Manufacturer Part Number: SDA4336
• Description: PLL Frequency Synthesizer, if Counter, 7 Bit ADC, 7 & 4 Bit DAC With Two Channel Digital Alignment
• Manufacturer: Infineon Technologies Corporation

1)
2)
3)
Note that the maximum t
mum t
SDA / SCL pins and the SDA /SCL bus lines without exceeding the maximum specified t
Semiconductor Group
LOW level input voltage
(SDA, SCL, BUS_ENA, BUS_MODE)
HIGH level input voltage
(SDA, SCL, BUS_ENA, BUS_MODE)
Pulse widh of spikes which must be suppressed by the
input filter
LOW level output voltage 3mA sink current (SDA)
Output fall time from V
tance from 10pF to 400pFwith up to 3mA
SCL clock frequency
Bus free time between a STOP and START condition
Hold time (repeated) START condition. After this
period, the first clock pulse is generated.
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Data hold time
Data set -up time
Rise, fall time of both SDA and SCL signals
Set-up time for STOP condition
Capacitive load for each bus line
Setup time SCL to BUS_ENA
H-pulsewidth (BUS_ENA)
Parameter
C
only in I
only in 3W bus mode
b
= capacitance of one bus line in pF.
OF
for the output stages (250ns).This allows series protection resistors to be connected between the
2
C bus mode
IHmin
F
for the SDA and SCL bus lines quoted at 300ns is longer than the specified maxi-
to V
2)
ILmax
1)
with a bus capaci-
1)
1)
Specification
30
1)
V
V
t
V
t
f
t
t
t
t
t
t
t
t
t
C
t
t
Symbol
SP
OF
SCL
BUF
HO.STA
LOW
HIGH
SU.STA
HD.DAT
SU.DAT
R
SU.STO
SU.SCLEN
WHEN
IL
IH
OL
b
, t
F
min.
-0.5
2.10
0
0
20+0.1C
0
1.3
0.6
1.3
0.6
0.6
0
100
20+0.1C
0.6
0.6
0.6
Limit Values
b
b
3)
3)
max.
0.90
5.50
50
0.40
250
400
300
400
F
.
SDA 4336
V
V
ns
V
ns
kHz
us
us
us
us
us
ns
ns
ns
us
pF
us
us
Unit
21.5.99