SDA9188-3X Infineon Technologies Corporation, SDA9188-3X Datasheet - Page 9

• Manufacturer Part Number: SDA9188-3X
• Description: Picture-in-picture Processor With On-chip PLL
• Manufacturer: Infineon Technologies Corporation

Position TV Standard (Parent)
3
3
3
3
Pixel data related to positive HSP edge
Line data related to positive VSP edge
* If the System is in the 50/60 Hz mixed mode RDV in Register 2 is forced to the logical “0“ state.
If FRWV is set to “0“ during the INT Mode the inset position will be shifted by one line.
The width of the borderframe is depending on the programming of the bits FRWV and FRWH (in
Register 5) 3 or 2 lines and 6 or 4 pixels.
The pixels and line number of the inset picture depend on the standard of the inset channel and on
the selected picture size.
Table 1
Inset Picture Size
Picture
Size
1/9
1/9
1/16
1/16
Interpolation of Chrominance Data Rate to Luminance Data Rate
To avoid chrominance artifacts after D/A conversion and for digital RGB conversion, the data rate
of the chrominance signals is quadrupled in order to match the luminance data rate. This is done by
repeating the chrominance data twice followed by low-pass filtering.
Semiconductor Group
(Frame Line Number)
625
525 *
625
525 *
TV Standard (Inset)
(Frame Line Number)
625
525
625
525
Picture
Size
1/9
1/9
1/16
1/16
Y
212
212
160
160
9
Pixel Number P
NINT
365
293
409
333
U
53
53
40
40
Location of Top Left Corner Point
for FRWH = 1, FRWV = 1
TV Line
(FL)
V
53
53
40
40
INT
183
147
205
167
Line Number L
88
76
66
57
SDA 9188-3X
Pixel
(FP)
448
448
502
502