SDA9254-2 Infineon Technologies Corporation, SDA9254-2 Datasheet - Page 8

• Manufacturer Part Number: SDA9254-2
• Description: 2.6mb Dynamic Sequential Access Memory For Television Applications (tv-sam) With On-chip Noise Reduction Filter
• Manufacturer: Infineon Technologies Corporation

Data Output A (SQA, SCA, OEA)
Data is shifted out through the serial port A (SQA0 … SQA11) at the rising edge of the shift clock
SCA. After 16 clock cycles new data have to be transferred from latch A to shift register A.
Otherwise data values are cyclically repeated.
Via the output enable OEA the output buffers can be switched into tristate.
The shift clock SCA may be completely independent on the shift clock for port B and C (SCB).
Memory Output (Port B, SCB)
Data is shifted out through the serial port B at the rising edge of the shift clock SCB. After 16 clock
cycles new data have to be transferred from latch B to shift register B. Otherwise data values are
cyclically repeated. The shift clock SCB is also used for the input port C.
Refresh
Either 256 refresh cycles (refresh with external row address) or read/write cycles on 212
consecutive row addresses beginning with address 0 have to be executed within an 16 ms interval
to maintain the data in the memory arrays.
A refresh with internal row adress is determined by the mode control bits, see “Addressing and
Mode Control”. In this refresh mode, the row and column addresses are ignored (see diagram 6a
and 6b).
Initialization
The device incorporates an on-chip substrate bias generator as well as dynamic circuitry. Therefore
an initial pause of 200 s is required after power on, followed by eight RE-cycles before proper
device operation is achieved.
Typical Memory Cycle Sequence
A typical application of the TV-SAM is a real-time noise reduction filtering combined with flicker
reduction. This can be achieved, for example, by writing and reading with 13.5-MHz clock rate via
port C and B and by simultaneously reading port A with 27-MHz double speed clock. A main cycle
of 4 consecutive RE cycles of transfer is needed:
Each transfer cycle is preceeded by an address cycle as shown in the diagram page 6:
For the clock rates mentioned this means a serial cycle time of 74 ns at port B and C and 37 ns at
port A. The addressing cycle time for each port is given by 16 times the serial data rate. Thus we
have an addressing cycle time of approx. 1184 ns for port B and port C. The address for port A must
be loaded every 592 ns. Since all addresses are shifted in sequentially, a RE cycle time of approx.
296 ns is necessary.
Semiconductor Group
1st.
2nd.
3rd.
4th.
RE-cycle:
RE-cycle:
RE-cycle:
RE-cycle:
Read transfer from memory to latch A
Read transfer from memory to latch B
Same as 1st. RE cycle
Write transfer from latch C to memory
8
SDA 9254-2
1998-01-16