SDA9290-6 Infineon Technologies Corporation, SDA9290-6 Datasheet
SDA9290-6
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SDA9290-6 Summary of contents
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Picture Processor Preliminary Data Features • Noise and cross color reduction by field - or frame recursive filtering • Adjustment of degree of noise reduction • Automatic adaption to signal quality during vertical blanking • Pixel adaptive movement detection • ...
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The necessary decimation and interpolation operations are activated automatically when the format is set. Together with a corresponding Memory Sync Controller (SDA 9220) it enables functions like multi-picture, tuner scanning, picture-in-still and still-in-picture. The different modes can be activated by ...
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A picture signal with reduced noise and cross-color appears on the output of the IIP for further processing. The signal will be forwarded via blocks MUXI and MUXO to the picture memories through the outputs (YQ0-YQ7 and UVQO-UVQ7 respectively). The ...
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CVBS BLN VS SDA 9290-6 LINE 000 (4) (Default) 001 (0) 010 (1) 011 (2) 100 (3) 101 (5) 110 (6) 111 (7) SDA 9290-5 312 313 BLN VS SDA 9290-6 LINE 000 (4) (Default) 001 (0) 010 ...
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C Bus Interface Bus interface configured as a “slave receiver” is used for programming the different functions 2 and modes of the picture processor. Via this interface up to four registers can be written according ...
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Register This control register sets the operating mode of the picture processor. R0: Bits D7, D6: Mode Normal Multi-picture (MP) Still-in-picture (SIP) Picture-in still (PIS) Bit D5: MPP: Narrow Frame Without narrow frame With narrow frame Bit D4: No function; ...
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Specialities Split Screen Display For demonstration purposes the noise reduction can be disabled for half of the picture by means of I C-Bus register R0, bit D3. In this way a direct comparison is possible 2 between a noise-reduced (filtered) ...
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Register This control register sets the frame luminance for multi-picture and the R1: threshold SL for S/N adaptation. Bits D7-D5: Frame Luminance YF 0 black : : : : : : 7 white Bits D4-D0: Threshold SL (S/N adaptation) 0 ...
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Register This control register sets the threshold SU for S/N adaptation, and the R2: values for the line counter. Noise Measurement: Decoded Values of the Line Counter LINE2 Bits D7-D5 Bits D4-D0: Threshold ...
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Register This register is for testing. certain S/N classes and filter coefficients for the R3: motion detector can be firmly set. Bits D7-D5: S/N Class Automatic adaptation Class 0 Class 1 Class 2 Bits D4-D0: Filter Coefficient Motion detector ON ...
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GND 4:1:1 8 DEMUXS Decimation UVI YS, USVS DREQ Clock LL3X Generation 16 YS BLN Control- VS1 8 Signals LLIN LLSEL FSI 2 FSBQ C Bus SDA Receiver SCL DEMUXR 8 UVB YR , ...
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GND 10 UVB0 11 UVB1 12 UVB2 13 UVB3 14 UVB4 15 UVB5 16 17 UVB6 UVB7 18 YB0 19 YB1 20 YB2 21 YB3 22 YB4 23 YB5 24 YB6 25 YB7 ...
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Pin Definitions and Functions Pin No. Symbol Function V 1 Positive supply DD voltage (+ 5 V) 2-9 UVQ7 … Data outputs UVQ0 10 GND Ground 11-18 UVB0 … Back-channel UVB7 data outputs 19-26 YB0 … Back- channel YB7 data ...
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Pin Definitions and Functions (cont’d) Pin No. Symbol Function 53 FSBQ Selection of output format 54 FSI Selection of input format 55 CLKEN Connect test pin 2 Has to be grounded ( normal mode 56 SPEN Connect test ...
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Electrical Characteristics Absolute Maximum Ratings (all voltages are referred to GND) Parameter Ambient temperature Storage temperature Total power dissipation Supply voltage Input/output voltage Thermal resistance system-air Operating Range Supply voltage Supply current Ambient temperature Note: Stresses above those listed here ...
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Characteristics (all voltages are referred to GND) Parameter H-input voltage 1) L-input voltage 1) Input current 1) Input capacitance 1) (except BLN, LLIN) Input capacitance 1) (only BLN, LLIN) H-input voltage 2) L-input voltage 2) Input capacitance 2) Input current ...
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Characteristics (cont’d) (all voltages are referred to GND) Parameter Input Clock LL3X = 13.5 MHz (refer to figure 6) Cycle Fall time Rise time H-pulse width L-pulse width Change in rel to LLIN Input Clock LLIN (refer to figure 6) ...
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Characteristics (cont’d) (all voltages are referred to GND) Parameter Input Signal VS1 Setup time Hold time Cycle, 625 lines Cycle, 525 lines H-pulse width, 625 lines H-pulse width, 525 lines Input Signal DREQ Setup time Hold time H-pulse width Input ...
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Characteristics (cont’d) (all voltages are referred to GND) Parameter Output Signal (Data) YQ0 … YQ7, UVQ0 … UVQ7 (refer to figure 5) Hold time Delay time Note: The listed characteristics are ensured over the operating range of the integrated circuit. ...
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GND SDA SCL DD 13.5 MHz 13.5 MHz UVB UVI SDA 9290-6 13.5 MHz 13.5 MHz UVQ FSBQ FSI BLN LLIN LLSEL VS1 DREQ LL3X V DD DREQ ...
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Input Clocks LL3X, LLIN Input Signals Output Signals Figure 5 Timing Diagram Semiconductor Group T LLIN SDA 9290-6 ,T LL3X t t THL WL TLH UET02221 2.0V 0.8V ...
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Input Clock Reference Clock LL3X Output Reference Clock Output Signal Input Reference Clock t Input Signal Figure 6 Timing Diagram Semiconductor Group T LLIN THL THL ...
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HD, STA SDA t BUF SCL Stop Start Figure 7 Timing for I C Bus 2 Table 1 All values are referred to specified input levels Parameter Clock frequency Inactive time before start of new transmission Hold time for ...
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Pixels 208 Pixels 48 Pixels 204 Pixels Figure 8 Picture Formats for 9-Image Display Semiconductor Group 720 Pixels Without Frame 4 Pixels With Frame 24 SDA 9290-6 ...
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Table 2 Assignment of Signal and Pin Names Format 4:1:1 Y:7-Bit Signal Y:8-Bit Signal – ...
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Table 3 Assignment of Signal and Pin Names Format 4:2:2 Signal UV7 UV6 UV5 UV4 UV3 UV2 UV1 UV0 Semiconductor Group Picture Processor Input Back Channel Input YI7 YB7 YI6 YB6 YI5 ...
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Figure 9 Output Data Delay Times Semiconductor Group 27 SDA 9290-6 1997-07-22 ...
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Package Outlines P-LCC-68-1 (SMD) (Plastic Leaded Chip Carrier) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 28 SDA 9290-6 Dimensions in mm 1997-07-22 ...