AD1868 Analog Devices, AD1868 Datasheet - Page 6

• Manufacturer Part Number: AD1868
• Description: Single Supply Dual 18-Bit Audio DAC
• Manufacturer: Analog Devices

AD1868
The AD1868 eliminates the need for “False Ground” circuitry.
V
generated by the “False Ground.” As shown in Figure 8b, V
and V
channel. This permits a dc-coupled output signal path. This
eliminates ac-coupling capacitors and improves low frequency
performance. It should be noted that these bias outputs have
relatively high output impedance and will not drive output
currents larger than 100 A without degrading the specified
performance.
DISTORTION PERFORMANCE AND TESTING
The THD+N figure of an audio DAC represents the amount of
undesirable signal produced during reconstruction and playback
of an audio waveform. Therefore, the THD+N specification
provides a direct method to classify and choose an audio DAC
for a desired level of performance.
B
R and V
CLK
B
DR
DL
LR
LL
L may be used as the reference point in each output
Figure 8b. Circuitry Using Voltage Biases
1
2
3
4
5
6
7
8
B
L generate the required bias voltages previously
DL
LR
DGND
V
V
LL
CK
DR
MSB
MSB
L
B
R
AD1868
AGND
NRL
NRR
V
V
V
O
O
B
V
V
L
R
L
S
S
16
15
14
13
12
11
10
9
+ 5V
+ 5V
Figure 9. Control Signals
V
V
O
O
L
R
B
R
–6–
Figure 1 illustrates the typical THD+N versus frequency perfor-
mance of the AD1868. It is evident that the THD+N perfor-
mance of the AD1868 remains stable at all three levels through
a wide range of frequencies. A load impedance of at least 2 k is
recommended for best THD+N performance.
Analog Devices tests and grades all AD1868s on the basis of
THD+N performance. During the distortion test, a high speed
digital pattern generator transmits digital data to each channel
of the device under test. Eighteen-bit data is latched into the
DAC at 352.8 kHz (8 F
sine wave with 0 dB, –20 dB, and –60 dB amplitudes. A 4096-
point FFT calculates total harmonic distortion + noise,
signal-to-noise ratio, and D-range. No deglitchers or external
adjustments are used.
DIGITAL CIRCUIT CONSIDERATIONS
INPUT DATA
The AD1868 digital input port employs five signals: Data Left
(DL), Data Right (DR), Latch Left (LL), Latch Right (LR) and
Clock (CLK). DL and DR are the serial inputs for the left and
right DACs, respectively. Input data bits are clocked into the in-
put register on the rising edge of CLK. The falling edges of LL
and LR cause the last 18 bits which were clocked into the serial
registers to be shifted into the DACs, thereby updating the re-
spective DAC outputs. For systems using only a single latch sig-
nal, LL and LR may be connected together. For systems using
only one DATA signal, DR and DL may be connected together.
Data is transmitted to the AD1868 in a bit stream composed of
18-bit words with a serial, twos complement, MSB first format.
Left and right channels share the Clock (CLK) signal.
Figure 9 illustrates the general signal requirements for data
transfer for the AD1868.
S
). The test waveform is a 990.5 Hz
LSB
LSB
REV. A