IDT2305-1HDCGGI Integrated Device Technology, Inc., IDT2305-1HDCGGI Datasheet - Page 6

• Manufacturer Part Number: IDT2305-1HDCGGI
• Description: General PLL: 3.3V Zero Delay Clock Buffer
• Manufacturer: Integrated Device Technology, Inc.

loading can affect and adjust the input/output delay. The Output Load Difference diagram illustrates the PLL's relative loading with respect to the other
outputs that can adjust the Input-Output (I/O) Delay.
load equal to that on the other outputs in order to obtain true zero I/O Delay. If I/O Delay adjustments are needed, use the Output Load Difference diagram
to calculate loading differences between the CLKOUT pin and other outputs. For zero output-to-output skew, all outputs must be loaded equally.
IDT2305
3.3V ZERO DELAY CLOCK BUFFER
For designs utilizing zero I/O Delay, all outputs including CLKOUT must be equally loaded. Even if the output is not used, it must have a capacitive
All outputs should be uniformly loaded in order to achieve Zero I/O Delay. Since the CLKOUT pin is the internal feedback for the PLL, its relative
-1000
-1500
1500
1000
-500
500
0
REF TO CLKA/CLKB RELAY vs. OUTPUT LOAD DIFFERENCE BETWEEN CLKOUT PIN AND CLKA/CLKB PINS
-30
OUTPUT LOAD DIFFERENCE BETWEEN CLKOUT PIN AND CLKA/CLKB PINS (pF)
-25
-20
-15
-10
-5
6
0
COMMERCIALAND INDUSTRIAL TEMPERATURE RANGES
5
10
15
20
25
30