EPC16xxx Altera, EPC16xxx Datasheet - Page 14

• Manufacturer Part Number: EPC16xxx
• Description: (EPC4 / EPC8 / EPC16) Enhanced Configuration Devices
• Manufacturer: Altera

Functional Description
Figure 2–4. FPP Configuration with External Flash Interface
Notes to
(1)
(2)
(3)
(4)
2–14
Configuration Handbook, Volume 2
For external flash interface support in EPC8 enhanced configuration device, contact Altera Applications.
Pin A20 in EPC16 devices, pins A20 and A19 in EPC8 devices, and pins A20, A19, and A18 in EPC4 devices should
be left floating. These pins should not be connected to any signal, i.e., they are no-connect pins.
In the 100-pin PQFP package, you must externally connect the following pins: C-A0 to F-A0, C-A1 to F-A1, C-A15
to F-A15, C-A16 to F-A16, and BYTE # to V
100-pin PQFP and 88-pin Ultra FineLine BGA packages: C-RP# to F-RP#, C-WE# to F-WE#, TM1 to V
GND, and WP# to V
For PORSEL, PGM[], and EXCLK pin connections, refer to
N.C.
Figure
n
2–4:
MSEL
nCEO
APEX II Device
Stratix Series
CC
CONF_DONE
or
.
DATA[7..0]
nCONFIG
nSTATUS
Dynamic Configuration (Page Mode)
The dynamic configuration or page mode feature allows the enhanced
configuration device to store up to eight different sets of designs for all
the FPGAs in your system. You can then choose which page (set of
configuration files) the enhanced configuration device should use for
FPGA configuration.
DCLK
nCE
V
CC
GND
V
CC
CC
. Additionally, you must make the following pin connections in both
GND
V
CC
Enhanced Configuration
BYTE# (3)
WP#
TM1
WE#C
RP#C
DCLK
DATA[7..0]
OE
nCS
nINIT_CONF
C-A0 (3)
C-A1 (3)
C-A15 (3)
C-A16 (3)
TMO
Table
2–9.
Device
Note (1)
A[20..0] (2)
PGM[2..0]
DQ[15..0]
PORSEL
RY/BY#
EXCLK
VCCW
WE#F
A0-F
A1-F
A15-F
A16-F
RP#F
CE#
OE#
V
CC
(4)
(4)
(4)
PLD or Processor
WE#
RP#
A[20..0]
RY/BY#
CE#
OE#
DQ[15..0]
Altera Corporation
August 2005
CC
, TM0 to