VMMK-3113 Avago Technologies, VMMK-3113 Datasheet - Page 6

• Manufacturer Part Number: VMMK-3113
• Description: 2 - 6 Ghz Directional Detector In Smt Package
• Manufacturer: Avago Technologies

VMMK-3113 Biasing Information
Biasing and Operation
The VMMK-3113 is a 3 terminal device consisting of a
“through” 50 ohm line connecting directly between the RF
Input and RF Output ports, and a directional coupler with
a full wave detector that provides a dc output proportional
to RF power input. As with any high frequency device,
good grounding is required on the common port under
the device for it to produce low loss in the “through” mode.
A suggested PCB layout with appropriate grounding will
be cover later in the application section.
With only 3 terminals available, the DC bias and detected
voltage are internally dc coupled to the input and output
terminals respectively. The key to successful operation
of the VMMK-3113 is the use of low loss bias decoupling
networks connected to both the RF Input and the RF
Output ports. Figure 7 shows a simple biasing circuit.
The bias decoupling networks provide a low loss ac coupled
RF path to the device, a means of biasing the device on the
input, and a means of extracting the detected voltage on
the output of the device. Bias decoupling networks in the
2 to 6 GHz frequency range can be easily produced using
simple lumped resistors and lumped capacitors. All SMT
components are suggested to be of 0402 or 0201 size. The
detector needs two DC blocking caps, C1 and C2, on the
RFin
Figure 7. Biasing the VMMK-3113 Detector Module
6
Component
C1, C2
R1
R2
C3, C4
R3
Vb
C1
C3
R1
Description
2 pF to 8 pF
(Vb - 1.5) / 0.00015 Ω
10 kΩ
1 pF to 2 pF
External load resistor (optional)
bias
detector
R2
C4
C2
R3
RFout
Vdet
input and output ports. This can be accomplished by using
SMT capacitors with values chosen for the frequency of
operation; e.g. 3.9 pF is suggested for 3-5GHz operation
Nominal bias voltage of 1.5 V or 0.16 mA is required for
proper operation. Biasing on the input is by a way of a
large value resistor R1. Its value can be computed using
the following equation:
R1 = (Vb -1.5) / 0.00015
where Vb is the supply voltage.
Detected DC voltage is extracted on the output by a way
of a large value resistor R2, in the range of 10 kΩ. Bypassing
capacitors C3 and C4 are needed to prevent RF influence
on the dc lines. Suggested value for bypass capacitors is
1 pF.
At zero RF input power, and at 1.5 V supply bias, a nominal
62 mV offset voltage appears at the detected output port.
The internal output source resistance for the detector is
approximately 20 kΩ. Resistor R3 can be used as an
external load resistor for the detector. Its value can be
optimized for the desired Vout vs. RF input curve.
Figure 8 shows a photo of a VMMK-3113 populated PCB
used to obtain the Vdet vs. Input Power characterization
data from 2 to 6 GHz.
Figure 8. VMMK-3113 Charaterization Board
Pins:
GND
Vb
GND Cdet
GND