XC2C512 Xilinx, XC2C512 Datasheet

XC2C512

Manufacturer Part Number

XC2C512

Description

Coolrunner-ii CPLD

Manufacturer

Xilinx

Datasheet

1.XC2C512.pdf (26 pages)

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Download datasheet (211Kb)

DS096 (v2.5) January 30, 2005

Features

•

Refer to the CoolRunner™-II family data sheet for architec-

ture description.

DS096 (v2.5) January 30, 2005

Preliminary Product Specification

Optimized for 1.8V systems

Industry’s best 0.18 micron CMOS CPLD

Available in multiple package options

Advanced system features

As fast as 6.0 ns pin-to-pin delays

As low as 14 A quiescent current

Optimized architecture for effective logic synthesis

Multi-voltage I/O operation — 1.5V to 3.3V

208-pin PQFP with 173 user I/O

256-ball FT (1.0mm) BGA with 212 user I/O

324-ball FG (1.2mm) BGA with 270 user I/O

Pb-free available for all packages

Fastest in system programming

IEEE1149.1 JTAG Boundary Scan Test

Optional Schmitt-trigger input (per pin)

Unsurpassed low power management

Four seperate output banks

RealDigital 100% CMOS product term generation

Flexible clocking modes

Global signal options with macrocell control

Advanced design security

PLA architecture

Open-drain output option for Wired-OR and LED

drive

Optional bus-hold, 3-state or weak pullup on

selected I/O pins

Optional configurable grounds on unused I/Os

Mixed I/O voltages compatible with 1.5V, 1.8V,

2.5V, and 3.3V logic levels

Hot Pluggable

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

1.8V ISP using IEEE 1532 (JTAG) interface

DataGATE enable signal control

Optional DualEDGE triggered registers

Clock divider (divide by 2,4,6,8,10,12,14,16)

CoolCLOCK

Multiple global clocks with phase selection per

macrocell

Multiple global output enables

Global set/reset

Superior pinout retention

100% product term routability across function

block

SSTL2-1, SSTL3-1, and HSTL-1 I/O compatibility

www.xilinx.com

1-800-255-7778

XC2C512 CoolRunner-II CPLD

Preliminary Product Specification

Description

The CoolRunner-II 512-macrocell device is designed for

both high performance and low power applications. This

lends power savings to high-end communication equipment

and high speed to battery operated devices. Due to the low

power stand-by and dynamic operation, overall system reli-

ability is improved

This device consists of thirty two Function Blocks inter-con-

nected by a low power Advanced Interconnect Matrix (AIM).

The AIM feeds 40 true and complement inputs to each

Function Block. The Function Blocks consist of a 40 by 56

P-term PLA and 16 macrocells which contain numerous

configuration bits that allow for combinational or registered

modes of operation.

Additionally, these registers can be globally reset or preset

and configured as a D or T flip-flop or as a D latch. There

are also multiple clock signals, both global and local product

term types, configured on a per macrocell basis. Output pin

configurations include slew rate limit, bus hold, pull-up,

open drain and programmable grounds. A Schmitt-trigger

input is available on a per input pin basis. In addition to stor-

ing macrocell output states, the macrocell registers may be

configured as "direct input" registers to store signals directly

from input pins.

Clocking is available on a global or Function Block basis.

Three global clocks are available for all Function Blocks as

a synchronous clock source. Macrocell registers can be

individually configured to power up to the zero or one state.

A global set/reset control line is also available to asynchro-

nously set or reset selected registers during operation.

Additional local clock, synchronous clock-enable, asyncho-

nous set/reset and output enable signals can be formed

using product terms on a per-macrocell or per-Function

Block basis.

A DualEDGE flip-flop feature is also available on a per mac-

rocell basis. This feature allows high performance synchro-

nous operation based on lower frequency clocking to help

reduce the total power consumption of the device.

Circuitry has also been included to divide one externally

supplied global clock (GCK2) by eight different selections.

This yields divide by even and odd clock frequencies.

The use of the clock divide (division by 2) and DualEDGE

flip-flop gives the resultant CoolCLOCK feature.

DataGATE is a method to selectively disable inputs of the

CPLD that are not of interest during certain points in time.

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