MT28F160C34 Micron Technology, MT28F160C34 Datasheet - Page 12

• Manufacturer Part Number: MT28F160C34
• Description: FLASH MEMORY
• Manufacturer: Micron Technology

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be read from a block other than the one being erased. To
resume the ERASE operation, an ERASE RESUME com-
mand (D0h) must be issued to cause the CSM to clear the
suspend state previously set. It is also possible that an
ERASE in any block can be suspended and a WRITE to
another block can be initiated. After the completion of
WRITE, the ERASE can be resumed by writing an ERASE
RESUME command (see Figure 6). It is also possible to
suspend the WRITE operation and read from another
block.
AUTOMATIC POWER-SAVING MODE
when the device is not accessed while in the active mode.
During this time, the device switches to the automatic
power saving (APS) mode. When the device switches to
this mode, I
entered automatically if no address or control lines toggle
within approximately a 300ns time-out period. At least
one transition on CE# must occur after power-up to acti-
vate this mode’s availability. The device remains in this
mode and the I/O lines retain the data from the last
access until a new read address is issued or another
operation is initiated.
RESET/ DEEP POWER-DOWN MODE
by using a special ball, RP#, to disable internal device
circuitry. When RP# is at a logic LOW level of 0.0V ±0.2V,
a much lower I
cally 1µA. This is important in portable applications where
extended battery life is a major concern.
power-down mode. A minimum of
a CSM command can be recognized. With RP# at ground,
the WSM is reset and the status register is cleared, effec-
tively eliminating accidental programming to the array
during system reset. After restoration of power, the de-
vice will be disabled until RP# is returned to V
tion, the device powers down and becomes nonfunc-
tional. Data being written or erased at that time becomes
invalid or indeterminate, requiring that the operation be
performed again after power restoration. When RP# is set
at logic LOW, all internal circuits will be reset. Setting RP#
LOW during a PROGRAM or ERASE operation is not rec-
ommended.
OTP MODE
mable) area. There are 64 bits that are programmed at the
factory with a unique 64-bit code that is not modifiable.
The other 64-bit OTP area is left blank to program for
1 Meg x 16 3V Enhanced+ Boot Block Flash Memory
MT28F160C34_3.p65 – Rev. 3, Pub. 8/01
4
U
If RP# goes LOW during a PROGRAM or ERASE opera-
Substantial power savings are realized during periods
Very low levels of power consumption can be attained
A recovery time is required when exiting from deep
The device has 128 bits of OTP (one time program-
.com
CC
CC
is reduced to 1µA typically. This mode is
current consumption is achieved, typi-
t
RS is required before
3V ENHANCED+ BOOT BLOCK FLASH MEMORY
IH
.
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12
customer design requirements if needed. Protection of
the user-programmable, 64-bit contents is provided, af-
ter the area is programmed, by programming the lock bit.
be written, followed by two WRITE cycles of the normal
program sequences. When in the OTP mode, the WSM
programs the OTP area and not the array. During pro-
gramming, a read can acquire only the WSM status (sta-
tus register output). When the programming is complete,
the device remains in the OTP mode and only the status
can be read in the OTP area. Writing two “FFh” com-
mands exits the OTP mode and causes the device to go
into the read array mode. To read the OTP area after
programming, the OTP mode must be re-entered.
must be written, followed by a READ. Writing two “FFh”
commands exits the OTP mode and causes the device to
go into the read array mode.
can be programmed. The lock bit is at address 00040h
and is on DQ15. Once the lock bit is programmed to a “0,”
the 64-bit, user-programmable area is permanently pro-
tected (see Figure 3). The lock bit can be read in OTP
mode, as described above.
STANDBY MODE
level on CE# and RP# to enter the standby mode. In the
standby mode, the outputs are placed in the high-imped-
ance state. Applying a logic HIGH level (V
and RP# reduces the current to 1µA typically. If the device
is deselected during an ERASE operation or during pro-
gramming, the device continues to draw active current
until the operation is complete.
NOTE: 1. Always locked.
To program the OTP area, two “AFh” commands must
To read the OTP area contents, two “AFh” commands
After programming the 64-bit OTP area, the lock bit
I
CC
supply current is reduced by applying a logic HIGH
00000h
00002h
00004h
00006h
00020h
00022h
00024h
00026h
00040h
2. Locked by programming DQ15 at address 00040h.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DQ15
Factory-Programmed
OTP Area Map
User-Programmed
Figure 3
4 Words
4 Words
1 MEG x 16
2
©2001, Micron Technology, Inc.
1
ADVANCE
CC
Q) on CE#