MT9044 Mitel Networks Corporation, MT9044 Datasheet - Page 2

• Manufacturer Part Number: MT9044
• Description: T1/E1/OC3 System Synchronizer
• Manufacturer: Mitel Networks Corporation

MT9044
2
Pin Description
PLCC
23,31
OSCo
AVDD
Pin #
C1.5o
1,10,
7,28
OSCi
F16o
VDD
RSP
VSS
TSP
11
F0o
F8o
2
3
4
5
6
8
9
39,4,17
MQFP
Pin #
1,22
10
11
12
13
14
15
16
17
,25
7
8
9
40
41
42
43
44
2
3
5
18 19 20 21 22 23 24
6
5
4 3
Name
OSCo
TCLR
TRST
OSCi
F16o
SEC
TCK
MT9044
PRI
V
V
2
SS
DD
1
44
25 26 27 28
43
Ground. 0 Volts.
Test Clock (TTL Input): Provides the clock to the JTAG test logic. This pin is
internally pulled up to V
TIE Circuit Reset (TTL Input): A logic low at this input resets the Time Interval
Error (TIE) correction circuit resulting in a re-alignment of input phase with output
phase as shown in Figure 19. The TCLR pin should be held low for a minimum of
300ns. This pin is internally pulled down to VSS.
Test Reset (TTL Input): Asynchronously initializes the JTAG TAP controller by
putting it in the Test-Logic-Reset state. This pin is internally pulled down to VSS.
Secondary Reference (TTL Input). This is one of two (PRI & SEC) input
reference sources (falling edge) used for synchronization. One of three possible
frequencies (8kHz, 1.544MHzMHz, or 2.048MHz) may be used. The selection of
the input reference is based upon the MS1, MS2, LOS1, LOS2, RSEL, and GTi
control inputs (Automatic or Manual). This pin is internally pulled up to V
Primary Reference (TTL Input). See pin description for SEC. This pin is
internally pulled up to V
Positive Supply Voltage. +5V
Oscillator Master Clock (CMOS Output). For crystal operation, a 20MHz crystal
is connected from this pin to OSCi, see Figure 10. For clock oscillator operation,
this pin is left unconnected, see Figure 9.
Oscillator Master Clock (CMOS Input). For crystal operation, a 20MHz crystal is
connected from this pin to OSCo, see Figure 10. For clock oscillator operation, this
pin is connected to a clock source, see Figure 9.
Frame Pulse ST-BUS 8.192 Mb/s (CMOS Output). This is an 8kHz 61ns active
low framing pulse, which marks the beginning of an ST-BUS frame. This is typically
used for ST-BUS operation at 8.192 Mb/s. See Figure 20.
42
41
40
39
38
37
36
35
34
33
32
31
30
29
TEST
RSEL
TDO
MS1
MS2
LOS1
LOS2
GTo
VSS
GTi
HOLDOVER
Figure 2 - Pin Connections
DD
DD
.
.
OSCo
AVDD
C1.5o
OSCi
F16o
VDD
VSS
RSP
TSP
F0o
F8o
DC
Description
nominal.
10
11
1
2
3
4
5
6
7
8
9
12 13 14 15 16 17 18
44
43
42 41
MT9044AL
40
39
Advance Information
38
19 20 21 22
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
TEST
RSEL
TDO
MS1
MS2
LOS1
LOS2
GTo
VSS
GTi
HOLDOVER
DD
.