MT90863 Mitel Networks Corporation, MT90863 Datasheet - Page 4

• Manufacturer Part Number: MT90863
• Description: 3V Rate Conversion Digital Switch
• Manufacturer: Mitel Networks Corporation

MT90863
Pin Description (continued)
4
128 MQFP
108-115
118-125
98-105,
Pin#
128,
1-7
92
94
95
10
11
12
13
14
15
16
9
C8, B8, A8, C7,
B6, A5, B5, A4,
A2, B2, A1, C3,
C11, B12, B11,
A12, A11, B10,
C2, B1, D3, D2
B4, C4, A3, B3
A10, B9, A9,
B7, A7, A6,
144 BGA
Pin#
B13
A13
C12
C1
D1
G3
E2
E1
F2
F3
F1
STio16 - 23
STio24 - 31 Serial Input Streams 24 to 31 (5V Tolerant I/O). These pins are only
STio0 - 15
FEi16 - 23
FEi0 - 15
RESET
C4i/C8i
Name
TRST
TMS
TDO
TCK
C4o
F0o
TDI
IC1
IC2
HMVIP/CT Bus Clock (5V Tolerant Input): When HMVIP mode is
enabled, this pin accepts a 4.096MHz clock for HMVIP frame pulse
alignment. When CT Bus mode is enabled, it accepts a 8.192MHz
clock for CT frame pulse alignment.
Frame Pulse (5V Tolerant Output): A 244ns wide negative frame
pulse that is phase locked to the master frame pulse (F0i).
C4 Clock (5V Tolerant Output): A 4.096MHz clock that is phase
locked to the master clock (C16i).
Serial Input Streams 0 to 15 / Frame Evaluation Inputs 0 to 15 (5V
Tolerant I/O). In 2Mb/s and HMVIP modes, these pins accept serial
TDM data streams at 2.048 Mb/s with 32 channels per stream. In 4Mb/
s or 8Mb/s mode, these pins accept serial TDM data streams at 4.096
or 8.192 Mb/s with 64 or 128 channels per stream respectively. In
Frame Evaluation Mode (FEM), they are frame evaluation inputs.
Serial Input Streams 16 to 23 (5V Tolerant I/O). In 2Mb/s or 4Mb/s
mode, these pins accept serial TDM data streams at 2.048 or 4.096
Mb/s with 32 or 64 channels per stream respectively. In HMVIP mode,
these pins have a data rate of 8.192Mb/s with 128 channels per
stream. In Frame Evaluation Mode (FEM), they are frame evaluation
inputs.
used for 2Mb/s or 4Mb/s mode. They accept serial TDM data streams
at 2.048 or 4.096 Mb/s with 32 or 64 channels per stream respectively.
Test Mode Select (3.3V Input with internal pull-up): JTAG signal
that controls the state transitions of the TAP controller.
Test Serial Data In (3.3V Input with internal pull-up): JTAG serial
test instructions and data are shifted in on this pin.
Test Serial Data Out (3.3V Output): JTAG serial data is output on this
pin on the falling edge of TCK. This pin is held in a high impedance
state when JTAG scan is not enabled.
Test Clock (5V Tolerant Input): Provides the clock to the JTAG test
logic.
Test Reset (3.3 V Input with internal pull-up): Asynchronously
initializes the JTAG TAP controller by putting it in the Test-Logic-Reset
state. This pin should be pulsed low on power-up, or held low
continuously, to ensure that the MT90863 is in the normal operation
mode.
Internal Connection 1 (3.3V Input with internal pull-down):
Connect to V
Device Reset (5V Tolerant Input): This input (active LOW) puts the
MT90863 in its reset state. This clears the device’s internal counters
and registers. It also brings microport data bus STio0 - 31 and STo0 -
15 to a high impedance state.
Internal Connection 2 (3.3V Input):
Connect to V
SS
SS
for normal operation.
for normal operation.
Description
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