MT9094 Mitel Networks Corporation, MT9094 Datasheet - Page 16

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MT9094

Manufacturer Part Number
MT9094
Description
ISO2-CMOS ST-BUS FAMILY Digital Telephone (DPhone-II)
Manufacturer
Mitel Networks Corporation
Datasheet

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MT9094
Note: Bits marked "-" are reserved bits and should be written with logic "0".
7-60
Timing Control Register
Loop-back Register
All bits active high:
Ch
Ch
LB
LB
2
1
io
oi
EN and Ch
EN
Active high enables data from the ST-BUS input to be looped back to the ST-BUS output directly at the pins. The DSTo
Active high enables data from ST-BUS output to be looped back to the ST-BUS input directly at the pins.
tri-state driver must also be enabled using one of the channel enable signals.
3
EN
-
Channels 2 and 3 are the B1 and B2 channels, respectively. PCM associated with the DSP, Filter/CODEC and trans-
Transmit B1 and B2 data on DSTo
Receive B1 and B2 data on DSTi
Channel 1 conveys the control/status information for the layer 1 transceiver. The full 64kb/s bandwidth is available and
ducer audio paths is conveyed in one of these channels as selected in the timing control register.
is assigned according to which transceiver is being used. Consult the data sheets for the transceiver selected. When
high register data is transmitted on DSTo. When low this timeslot is tri-stated on DSTo. Receive C-Channel data (DSTi)
is always routed to the register regardless of this control bit's logic state.
-
7
7
When high PCM from the Filter/CODEC and DSP is transmitted on DSTo in the associated channel. When low
DSTo is forced to logic 0 for the corresponding timeslot. If both Ch
channel 2.
When enabled PCM from DSTi is routed to the DSP and Filter/CODEC in the associated channel. If both Ch
and Ch
LBio
-
6
6
3
EN are enabled, data input defaults to channel 2.
LBoi
5
5
-
-
-
4
4
CH
-
3
3
3
EN
CH
-
2
2
2
EN
CH
-
1
1
1
EN
ADDRESS = 16h WRITE/READ VERIFY
ADDRESS = 15h WRITE/READ VERIFY
ADDRESSES 17h - 1Ch are RESERVED
-
0
2
-
0
EN and Ch
3
EN are enabled, data defaults to
Power Reset Value
Power Reset Value
X00X XXXX
XX0X 0000
2
EN

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