MT9M413 Micron Technology, MT9M413 Datasheet - Page 20

• Manufacturer Part Number: MT9M413
• Description: 1.3-MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
• Manufacturer: Micron Technology

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Analog Voltage Setting Considerations
in the “AC Electrical Characteristics” on page 18 should
be the starting point for setting the analog voltages.
Additionally, it is useful to refer to the “Signal Path Dia-
gram” on page 3 that indicates how the analog voltages
affect the image. Other considerations are as follows:
VREF1 This ADC reference voltage can also be utilized
as a gain. A lower value will increase gain, but also
results in amplification of nonuniformities.
VREF4: Should always be set to ¼ of VREF1.
VREF2 Reference used for the ADC calibration to
remove column-wise FPN. If set much lower than the
typical value there is a possibility that some column
nonuniformities will not be corrected. Setting higher
than typical will result in more column-wise FPN.
When debugging analog voltage settings it may be use-
ful to temporarily set VREF2 to zero, effectively stop-
ping the ADC calibration process and adjusting the
VLN/VLP settings.
VLN1 The on-chip generated voltage should be used
as the starting point; increasing above typical will
result in an increase in current, speed, and FPN in the
first buffer.
VLN2 The on-chip generated voltage should be used
as the starting point. Controls the current in the ADC
comparators (there is a safe range where this voltage
has no effect); above or below this range will cause the
comparators to fail. If vertical white stripes appear in
the center of the imaging area or random white spots
appear in contour areas, it is an indication that VLN2
needs to be adjusted.
VLP The on-chip generated voltage should be used as
the starting point.
VRST_PIX Voltage for pixel reset. If this is too close to
VAA the image will be degraded and is not recom-
mended to be above 2.9V, but if it is set too low the
pixel dynamic range may decrease. In the initial pre-
production version of the MI-MV13 the number of
defects increased with reduced VRST_PIX so it was rec-
09005aef806807ca
MT9M413C36STC.fm - Ver. 3.0 1/04 EN
The values suggested in the Typical Values column
1.3-MEGAPIXEL CMOS ACTIVE-PIXEL
20
ommended to keep this as high as possible. If high
VRST_PIX resulted in vertical FPN it was compensated
via adjustments to VLN1 and VLN2.
VREF3 and VCLAMP3 These control the offset as
shown in the “Signal Path Diagram” on page 3. This
must be enabled via DARK_OFF_EN_N; Offset is ~
(VREF3-VCLAMP3)/20.
Figure 14: Clock to Data Propagation
SYSCLK
DOUT (99:0)
INPUT
Figure 13: Set Up and Hold Time
SYSCLK
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DIGITAL IMAGE SENSOR
tr
Delay
Tplh, Tphl
T
setup
©2004 Micron Technology, Inc. All rights reserved.
T
hold